Line edge roughness frequency analysis during pattern transfer in semiconductor fabrication

Double patterning technology has now proved its efficiency to go beyond the standard lithographic printing limits and address the resolution requirements of the sub-20 nm technological node. However, some data are still lacking regarding the characterization of line edge/width roughness (LER/LWR) in such integration. In this work, a detailed spectral analysis of the sidewall roughness evolution during a resist-core self-aligned double patterning (SADP) integration is presented. A 20 nm half-pitch SADP process using photoresist as the core material, and SiO2 deposited by plasma enhanced atomic layer deposition as the spacer material is developed. The LER and LWR have been characterized at each technological step involved in the SADP process flow, using a power spectral density fitting method, which provides a full description of the sidewalls roughness with the estimation of noise-free roughness amplitude (σ), correlation length (ξ), and roughness exponent (α). Results show that the SADP process allows to decrease drastically the LWR and LER amplitudes down to 2.0 nm corresponding to a reduction of about 70% and 50%, respectively, compared to the initial resist patterns. Although the SADP concept generates two asymmetric populations of lines, the final features present similar LWR, LERleft, and LERright parameters. The study also highlights the effectiveness of the SADP concept to decrease critical dimension variation and low-frequency LWR components to values inferior to 1 nm, which is an outstanding improvement compared to other single or double patterning techniques. However, this work brings out that the deposition process is the key step to ensure successful resist-core SADP integration. It must not only be as conformal as possible but also preserve the square shape of the core material. It is shown that the resist lateral erosion occurring during the deposition step introduces some random resist sidewalls angles that contribute to the formation of short range roughness during the spacer etching transfer, resulting in residual LWR mainly composed of high-and medium-frequency components. Contrary to LWR, the beneficial impact of the conformal spacer deposition on low-frequency roughness components has rather no effect on LER. The LER parameters after spacer etching mainly depend on the core ones prior to deposition. LER low-frequency components remain a key issue to address for an optimized integration.

show abstract

Line edge roughness frequency analysis during pattern transfer in semiconductor fabrication

Cited by 5 publications

References 25 publications

Nanoscale Transistor Variability Modeling: How Simple Physics Enables a Powerful Prediction Platform

Nanoscale Transistor Variability Modeling: How Simple Physics Enables a Powerful Prediction Platform

An Analytical Model to Estimate ${V}_{T}$ Distribution of Partially Correlated Fin Edges in FinFETs Due to Fin-Edge Roughness

Spectral analysis of sidewall roughness during resist-core self-aligned double patterning integration

Contact Info

Product

Resources

About