Line-edge roughness induced single event transient variation in SOI FinFETs

Wu, Wenyi; An, Xia; Jiang, Xiaobo; Chen, Yehua; Liu, Jingjing; Zhang, Xing; Huang, Ru

doi:10.1088/1674-4926/36/11/114001

Cited by 10 publications

(8 citation statements)

References 9 publications

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“…With the aggressive scaling down of MuGFETs, BTI and HCI are not the only reliability issues in the MuGFET technologies. Reliability topics like electromigration [68,69] , device-todevice variation [70,71] , cycle-to-cycle variation [70] , random telegraph noise [72,73] , dielectric breakdown characteristics [74,75] etc. are also get more severe.…”

Section: Bias Temperature Instability and Hot Carrier Injectionmentioning

confidence: 99%

The past and future of multi-gate field-effect transistors: Process challenges and reliability issues

Sun

Zhang

et al. 2021

J. Semicond.

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This work reviews the state-of-the art multi-gate field-effect transistor (MuGFET) process technologies and compares the device performance and reliability characteristics of the MuGFETs with the planar Si CMOS devices. Owing to the 3D wrapped gate structure, MuGFETs can suppress the SCEs and improve the ON-current performance due to the volume inversion of the channel region. As the Si CMOS technology pioneers to sub-10 nm nodes, the process challenges in terms of lithography capability, process integration controversies, performance variability etc. were also discussed in this work. Due to the severe self-heating effect in the MuGFETs, the ballistic transport and reliability characteristics were investigated. Future alternatives for the current Si MuGFET technology were discussed at the end of the paper. More work needs to be done to realize novel high mobility channel MuGFETs with better performance and reliability.

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Section: Bias Temperature Instability and Hot Carrier Injectionmentioning

confidence: 99%

The past and future of multi-gate field-effect transistors: Process challenges and reliability issues

Sun

Zhang

et al. 2021

J. Semicond.

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“…When an energetic particle strikes into the sensitive area of FinFET device, single event transient (SET) may be occurred by the diffusion and drift effects 1 – 3 . Due to the reduced parasitic capacitance from silicon-on- insulator (SOI) technology and the improved tolerance from thin fins, FinFET, with narrow silicon fin, combined with SOI and high k /metal gate stacked technology, brings benefits to radiation effects 2 – 4 . It was indicated that single event responses of FinFET may be significantly affected by ion hit angular, position and energy, supply voltage, device size and number of fins, technology node, and so on 3 , 5 – 7 .…”

Section: Introductionmentioning

confidence: 99%

Single event response of ferroelectric spacer engineered SOI FinFET at 14 nm technology node

Liu

Zhu

2023

Sci Rep

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The impact of spacer on the single event response of SOI FinFET at 14 nm technology node is investigated. Based on the device TCAD model, well-calibrated by the experimental data, it is found that the spacer presents the enhancement on single event transient (SET) compared with no spacer configuration. For single spacer configuration, due to enhanced gate control capability and fringing field, the increments in SET current peak and collected charge for HfO2 are the least with 2.21%, 0.97%, respectively. Four possible dual ferroelectric spacer configurations are proposed. The placement of ferroelectric spacer at S side and HfO2 spacer at D side brings to weaken SET with the variation in current peak and collected charge by 6.93%, 1.86%, respectively. The reason may be its enhanced gate controllability over the S/D extension region, which improves the driven current. With linear energy transfer increasing, SET current peak and collected charge present the trend of increase while the bipolar amplification coefficient reduces.

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“…Recently, many efforts have been devoted to investigate the single event behavior in FinFET technology [6][7][8][9][10][11][12][13]. El-Mamouni et al compare the transient current between bulk and SOI FinFET induced by heavy ion and more collected charges in bulk FinFET are demonstrated [11].…”

Section: Introductionmentioning

confidence: 99%

Influence of fin width on single event-upset characteristics of FinFET SRAM

Li¹,

An²,

Ren³

et al. 2020

Semicond. Sci. Technol.

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In this paper, the influence of fin width on single event-upset (SEU) characteristics of 14 nm bulk and SOI FinFET 6 T SRAM is investigated by 3D TCAD mixed-mode simulation. Simulation results show that the threshold linear energy transfer (LET th ) of SOI FinFET SRAM is larger than bulk FinFET SRAM. Moreover, the LET th of bulk and SOI FinFET SRAM increases with fin width scaling, and LET th of SOI FinFET SRAM increases more rapidly than bulk FinFET counterpart. The results indicate that bulk and SOI FinFET SRAM would be more immune to SEU response as fin width scales down, especially for SOI FinFET SRAM. Furthermore, the effect of fin width on critical charge and collected charge are explored to explain the fin width dependence of LET th in FinFET SRAM. Both critical charge and collected charge decrease with fin width reducing. However, the collected charge decreases much faster, which becomes the dominant factor for single event sensitivity of FinFET SRAM with fin width scaling.

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Line-edge roughness induced single event transient variation in SOI FinFETs

Cited by 10 publications

References 9 publications

The past and future of multi-gate field-effect transistors: Process challenges and reliability issues

The past and future of multi-gate field-effect transistors: Process challenges and reliability issues

Single event response of ferroelectric spacer engineered SOI FinFET at 14 nm technology node

Influence of fin width on single event-upset characteristics of FinFET SRAM

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