Linearity Analysis of CMOS Parametric Upconverters

Abstract

This paper applies a conversion matrix approach to the linearity analysis of a varactorbased 36-GHz CMOS parametric upconverter. The nonlinear model of the upconverter is explained and derived. The comparison between the measurements, simulations, and theoretical calculation is presented to show excellent agreements: 0.5-and 1.5-dB differences in conversion gains for lower-sideband and uppersideband upconversion, and less than 2.9-dB in both IIP 2 and IIP 3 when converting a 1-GHz signal to 36-GHz output.