2012
DOI: 10.1016/j.mee.2012.04.013
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Linking EUV lithography line edge roughness and 16nm NAND memory performance

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Cited by 13 publications
(5 citation statements)
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“…To avoid misunderstanding of LWR and pattern integrity, line edge roughness (LER) was proposed [4] which was able to quantify the aforementioned pattern distortion on individual sides of lines. Although it is still impossible to obtain the electrical performance at these patterning stages, engineers tried to link the LWR or LER to various transistor characteristics with relationships that imply performance tendencies [5][6][7][8][9][10].…”
Section: Supportivenessmentioning
confidence: 99%
“…To avoid misunderstanding of LWR and pattern integrity, line edge roughness (LER) was proposed [4] which was able to quantify the aforementioned pattern distortion on individual sides of lines. Although it is still impossible to obtain the electrical performance at these patterning stages, engineers tried to link the LWR or LER to various transistor characteristics with relationships that imply performance tendencies [5][6][7][8][9][10].…”
Section: Supportivenessmentioning
confidence: 99%
“…Although literature has indicated potential relationships between pattern distortion and its EM performance [9][10][11][12][13], they failed to provide solutions to predict the results. Researchers also tried to establish related system and procedures to predict some responses of Archimedean spiral antennas through their fabrication features, results were incomplete due to impractical target design, non-optimized software and hardware modules, insufficient data, low confidence level of results, and non-integrated humanmachine interface (table 1) [14,15].…”
Section: Introductionmentioning
confidence: 99%
“…Furthermore, the high demand for microelectronics and nanoelectronic devices increases because they are highly-precious and used to control dimensional structures in wafer-scale manufacturing [17][18][19][20]. The device invention methodologies are already well known in electronic manufacture using silicon chips miniaturization on a large scale [21][22].…”
Section: Introductionmentioning
confidence: 99%