Liquid cooling for 3D-ICs

Shi, Bing; Srivastava, Ankur

doi:10.1109/igcc.2011.6008576

Cited by 5 publications

(4 citation statements)

References 43 publications

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“…This technology has the ability to cool areas with high heat density (as much as 700W/cm 22 ), and is therefore very appropriate for cooling 3D ICs. 3 Figure 4.1 shows a three-tier 3D IC. Each tier contains an active silicon layer (solid) which consists of functional units such as cores and memories which dissipates power.…”

Section: Microfluidic Coolingmentioning

confidence: 99%

“…3 shows the comparison of wirelength and micro-channel cooling power for the three approaches. In the table, "≤ T max " indicates if the achieved thermal profile satisfies the thermal constraint, MC first indicates the micro-channel first approach.Table 4.3 shows that using air cooling results in thermal violation for all power profiles, while micro-channels can provide sufficient cooling.…”

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confidence: 99%

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Srivastava

Sapatnekar

Shi

et al. 2014

Encyclopedia of Thermal Packaging

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Section: Microfluidic Coolingmentioning

confidence: 99%

mentioning

confidence: 99%

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Srivastava

Sapatnekar

Shi

et al. 2014

Encyclopedia of Thermal Packaging

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“…Micro-channel liquid cooling, which integrates micro-channel heat sinks into each tier of the 3D-IC and uses liquid flow to remove heat inside 3D chip can better address this problem. Many works have been done to investigate micro-channel based heat sink in 3D-IC, these works are summarized in [2].…”

Section: Introductionmentioning

confidence: 99%

Cooling of 3D-IC using non-uniform micro-channels and sensor based dynamic thermal management

Shi

Srivastava

2011

2011 49th Annual Allerton Conference on Communication, Control, and Computing (Allerton)

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The three dimensional integrated circuit (3D-IC) brings new challenges to chip thermal management due to its high power density. Micro-channel based liquid cooling shows great potential in removing high density heat in 3D circuits. The current micro-channel heat sink designs spread the entire surface to be cooled with micro-channels. This approach, though might provide sufficient cooling, requires quite high pumping power. In this paper, we investigate designing of nonuniformly distributed micro-channel cooling systems which provide sufficient cooling with less pumping power. Using the proposed non-uniform micro-channel heat sink, dynamic thermal management is also investigated by tuning the pressure drop across the micro-channels. The experiments show that, compared with the conventional design which spreads microchannels all over the chip, our non-uniform micro-channel design and thermal management achieves more than 70% pumping power savings.

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“…There is a significant research effort to tackle the power issue at different levels. At the software level thermal-aware task scheduling policies [23] can be implemented, while at the fabrication level, cooling techniques such as inter-layer micro-channel liquid cooling [22] and Thermal-TSVs(TTSV) [24], [25] can be exploited to remove the excessive heat. In this chapter, we do not propose any cooling or thermal management techniques, but we focus on exploring the power dissipation of 3D-LIN to ensure reliability.…”

Section: Power Analysismentioning

confidence: 99%

Configurable Low-Latency Interconnect for Multi-core Clusters

Beanato¹,

Loi²,

Micheli³

et al. 2013

VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design

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Abstract. Shared L1 memories are of interest for tightly-coupled processor clusters in programmable accelerators as they provide a convenient shared memory abstraction while avoiding cache coherence overheads. The performance of a shared-L1 memory critically depends on the architecture of the low-latency interconnect between processors and memory banks, which needs to provide ultra-fast access to the largest possible L1 working set. The advent of 3D technology provides new opportunities to improve the interconnect delay and the form factor. In this chapter we propose a network architecture, 3D-LIN, based on 3D integration technology. The network can be configured based on user specifications and technology constraints to provide fast access to L1 memories on multiple stacked dies. The extracted results from the physical synthesis of 3D-LIN permit to explore trade-offs between memory size and network latency from a planar design to multiple memory layers stacked on top of logic, evaluating the improvement in both form factor and latency.

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Liquid cooling for 3D-ICs

Cited by 5 publications

References 43 publications

Ongoing Efforts

Ongoing Efforts

Cooling of 3D-IC using non-uniform micro-channels and sensor based dynamic thermal management

Configurable Low-Latency Interconnect for Multi-core Clusters

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