LIRA-V: Lightweight Remote Attestation for Constrained RISC-V Devices

Abstract

This paper presents LIRA-V, a lightweight system for performing remote attestation between constrained devices using the RISC-V architecture. We propose using read-only memory and the RISC-V Physical Memory Protection (PMP) primitive to build a trust anchor for remote attestation and secure channel creation. Moreover, we propose a bi-directional attestation protocol for trusted device-to-device communication, which is subjected to formal symbolic verification using SCYTHER. We present the design, implementation and evaluation of LIRA-V using an off-the-shelf RISC-V microcontroller and present performance results to demonstrate its suitability. To our knowledge, we present the first remote attestation mechanism suitable for constrained RISC-V devices, with applications to the Internet of Things (IoT) and Cyber Physical Systems (CPS).

A TOCTOU Attack on DICE Attestation

“…These techniques usually use some form of deeply integrated hardware extensions of the Central Processing Unit (CPU). Further, regarding the time at which the attestation evidence is generated the attestation techniques can be classified in attestation with boot time evidence generation [28,53,60], attestation with on-request evidence generation [20,27,32,41,56] and attestation with self-initiated evidence generation [25,26,34].…”

“…Those techniques are applicable only when the communication channel between prover and verifier has constant delays, therefore they are not suitable for devices communicating over the Internet. Hybrid techniques, e.g., [20,27,32,41,56] have lower hardware cost than the hardware techniques and at the same time does not impose timing requirements on the communication as the software-based techniques which makes them the preferred choice for constrained IoT devices. These techniques usually use some form of deeply integrated hardware extensions of the Central Processing Unit (CPU).…”

Physical Fault Injection and Side-Channel Attacks on Mobile Devices: A Comprehensive Analysis

“…Such proposals could reflect possible commercial services and serve as future attack targets. Moreover, new TEEs and security mechanisms continue to be developed using the RISC-V open-source instruction set architecture [85,102,134,141]. The efficacy of SCAs and FIAs against these systems is another interesting future research direction, especially if RISC-V becomes increasingly used by mobile device OEMs.…”