Lithographic imaging-driven pattern edge placement errors at the 10-nm node

Abstract

As new microelectronic designs are being developed, the demands on image overlay and pattern dimension control are compounded by requirements that pattern edge placement errors (EPEs) be at a single-nanometer levels. Scanner performance plays a key role in determining location of the pattern edges at different device layers, not only through overlay but also through imaging performance. The imaging contributes to edge displacement through the variations of the image dimensions and by shifting the images from their target locations. We discuss various aspects of advanced image control relevant to a 10-nm node integrated circuit design. We review a range of issues of pattern edge placement directly linked to pattern imaging. We analyze the impact of different pattern design and scanner-related edge displacement drivers. We present two examples of imaging strategies to pattern logic device metal layer cuts. We analyze EPEs of the cut images resulting from optimized layout design and scanner setup, and we draw conclusions on edge placement control versus imaging performance requirements. Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 06/24/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx J. Micro/Nanolith. MEMS MOEMS 021402-8 Apr-Jun 2016 • Vol. 15(2) Tyminski et al.: Lithographic imaging-driven pattern edge placement errors at the 10-nm node Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 06/24/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx J. Micro/Nanolith. MEMS MOEMS 021402-10 Apr-Jun 2016 • Vol. 15(2) Tyminski et al.: Lithographic imaging-driven pattern edge placement errors at the 10-nm node Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 06/24/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

Review of scanning electron microscope-based overlay measurement beyond 3-nm node device

“…The effect seems to be mainly a slit size and pitch issue. This is widely known to be related to coma aberration fingerprint of the i-ArF scanner 16,17 but has not been simulated. Overlay error was caused by scanner aberration depending on a variability from tools and the illumination condition of the scanner, which is decided from the typical pattern feature.…”

“…The Opt-OL measurement results at after-develop inspection (ADI) were shifted due to scanner lens aberration depending on the pattern sizes of optical metrology targets, which are significantly larger than device patterns. [15][16][17][18][19] Wafer-induced shift (WIS) is introduced to account for the errors due to pattern asymmetry of the overlay targets. 20 It is induced by process steps such as etch 21 or chemicalmechanical polishing (CMP).…”

Overlay error statistics for multiple-exposure patterning

“…[25][26][27] No matter what it is called the combined effect of CD and overlay error is well known to the design community as a key variable that not only affects space between two features but also design constructs that require overlap and intersect area (IA) between two shapes. 28 Edge placement error [29][30][31][32] and relative edge placement error 33 are also terms that describe the effect of CD and overlay error together.…”