Lithographic plane review (LPR) for sub-32nm mask defect disposition

Tolani, Vikram; Peng, Danping; He, Lin; Hwa, George; Chang, Hsien-Min; Dai, Grace; Corcoran, Noel; Dam, Thuc; Pang, Liang; Tuo, Laurent C.; Chen, C. J.; Lai, Rick

doi:10.1117/12.864284

Cited by 9 publications

(6 citation statements)

References 3 publications

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“…Similar techniques have been developed and implemented in production of DUV masks for example, in transforming mask-plane inspection images to actinic aerial images to actual scanner illumination optics to resist print image [3], [4], [5], [6], [7], [8]. These have also been enabled by the development and calibration of optical and e-beam models to characterize masks, review systems, exposure systems, and wafer resist.…”

Section: Figure 1 Typical Euv Mask and Blank Hard-defectsmentioning

confidence: 96%

EUV mask absorber and multi-layer defect disposition techniques using computational lithography

Tolani

Satake

et al. 2011

SPIE Proceedings

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Many efforts in EUV are currently focused on detecting and reducing defects on blanks and patterned masks. Bumps and pits found on blank substrates are particularly of concern since these effectively cause phase change and often print severely under EUV conditions. With the current inspection of EUV blanks and patterned masks being primarily highresolution DUV or e-beam based, it becomes very challenging to assess the impact of the detected defects. Even with the realization of EUV AIMS TM , expected in 2014, the nature of the buried multi-layer defect in terms of its location, size, shape, and profile will always be uncertain.In this paper, we have demonstrated several techniques that can be used for EUV defect disposition both in short-and long-term. These techniques include use of SEM images for absorber-defect disposition, and AFM images for determining the printability of buried defects. In the case of absorber defects, the SEM image of the defect is processed through a novel contour-extraction algorithm which accurately extracts the contours of the defective and generates the contour of the reference patterns. The mask contours are then simulated in Luminescent's EUV Defect Printability Simulator (DPS), a fast and accurate EUV simulator, and the EUV aerial images subsequently analyzed in the Aerial Image Analyzer (AIA). For buried defects, models characterizing the growth of the multi-layer defect from substrate and multi-layer to the surface have been developed and can be calibrated in several ways, including using cross-sectional TEM profiles of buried defects. Using the calibrated buried defect growth model then, and the surface profile of the buried defect as indicated in the SEM and AFM images, the exact nature of the buried defect is "recovered". Knowing the profile of the buried pit or bump defect through the multi-layer then allows estimation of its printability impact in DPS. Furthermore, this also enables computing changes that could be then made to the absorber pattern in order to compensate for the buried defect printability, i.e., in Luminescent's Multi-layer Defect Compensation (MDC). This technique of inverting to the shape and height of the buried defect can also be refined later once EUV aerial images are available.While defectivity on EUV masks is currently the #1 concern in its high-volume adoption, disposition of the detected defects to EUV conditions is also very crucial. The proposed disposition techniques using Computation Lithography can be used in combination with print-tests to make the overall EUV mask defect handling flow manufacturable.

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Section: Figure 1 Typical Euv Mask and Blank Hard-defectsmentioning

confidence: 96%

EUV mask absorber and multi-layer defect disposition techniques using computational lithography

Tolani

Satake

et al. 2011

SPIE Proceedings

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“…Details of LAIPH LPR results and accuracy can be found from Luminescent joint papers with TSMC [13], Samsung [11], and Applied Materials [12]. Figure 15 shows four examples on contact layer from the joint papers with TSMC published at the same conference [13] -one MoSi extension on corner, one pin-dot in center, one clear intrusion in corner, and one over-sized contact.…”

Section: Figure 14 Laiph Litho Plan Review (Lpr) Workflowmentioning

confidence: 97%

“…Figure 15 shows four examples on contact layer from the joint papers with TSMC published at the same conference [13] -one MoSi extension on corner, one pin-dot in center, one clear intrusion in corner, and one over-sized contact. One can notice that all of these defects are recovered from the high resolution inspection image, in particular, the pin-dot defect, while it is not seen in the inspection image.…”

Section: Figure 14 Laiph Litho Plan Review (Lpr) Workflowmentioning

confidence: 99%

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Computational lithography and inspection (CLI) and its applications in mask inspection, metrology, review, and repair

Pang

Peng

et al. 2010

SPIE Proceedings

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At the most advanced technology nodes, such as 32nm, 22nm, and beyond, aggressive OPC and Sub-Resolution Assist Features (SRAFs) on the mask are essential for accurate on-wafer imaging; mask patterns generated by Inverse Lithography Technology (ILT) and Source Mask Optimization (SMO) may also be necessary for production. However, their use results in significantly increased mask complexity, making mask defect disposition more challenging than ever. Computational Lithography and Inspection (CLI) have broad applications in mask inspection, metrology, review, and repair, and provide additional information to assist the operator in making accurate and efficient decisions on defect disposition. In this paper these applications of CLI in mask inspection, off-line review, metrology, and repair are presented and discussed.

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“…Luminescent continued working on computational inspection and metrology technologies to enable mask inspection, mask review, and mask repair ready for ILT masks, until it was acquired by KLA in 2012, and TSMC EBO presented a number of papers together with Luminescent showing such capabilities deployed in production. [92][93][94][95][96][106][107][108][109][110][111][112][113][114] ILT was the topic of panel discussion at the SPIE Photomask Technology Conference for two consecutive years in 2015 and 2016. The industry also recognized the issue of using VSB mask writers to write curvilinear ILT masks.…”

Section: History Of Inverse Lithographymentioning

confidence: 99%

Inverse lithography technology: 30 years from concept to practical, full-chip reality

Pang

2021

J. Micro/Nanopattern. Mats. Metro.

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In lithography, optical proximity and process bias/effects need to be corrected to achieve the best wafer print. Efforts to correct for these effects started with a simple bias, adding a hammer head in line-ends to prevent line-end shortening. This first-generation correction was called rule-based optical proximity correction (OPC). Then, as chip feature sizes continued to shrink, OPC became more complicated and evolved to a model-based approach. Some extra patterns were added to masks, to improve the wafer process window, a measure of resilience to manufacturing variation. Around this time, the concept of inverse lithography technology (ILT), a mathematically rigorous inverse approach that determines the mask shapes that will produce the desired on-wafer results, was introduced. ILT has been explored and developed over the last three decades as the next generation of OPC, promising a solution to several challenges of advanced-node lithography, whether optical or extreme ultraviolet (EUV). Today, both OPC and ILT are part of an arsenal of lithography technologies called resolution enhancement technologies. Since OPC and ILT both involve computation, they are also considered as part of computational lithography. We explore the background and history of ILT and detail the significant milestones that have taken full-chip ILT from an academic concept to a practical production reality.

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Lithographic plane review (LPR) for sub-32nm mask defect disposition

Cited by 9 publications

References 3 publications

EUV mask absorber and multi-layer defect disposition techniques using computational lithography

EUV mask absorber and multi-layer defect disposition techniques using computational lithography

Computational lithography and inspection (CLI) and its applications in mask inspection, metrology, review, and repair

Inverse lithography technology: 30 years from concept to practical, full-chip reality

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