Lithography analysis of via-configurable transistor-array fabrics

Abstract

Regular fabrics are expected to mitigate manufacturing process variations, increasing the fabrication yield in deep sub-micron CMOS technologies. This paper presents an extensive analysis of lithography behaviour of transistor-array based regular fabrics. Four different approaches presented in the literature (VCC, INVA, VCLB and VCTA) have been evaluated through lithography simulations. The wellestablished concept of edge placement error (EPE) has been taken into account as lithography behavior metric.