Lithography-driven layout of logic cells for 65-nm node

Critical evaluation of photomask needs for competing 65-nm node RET options

“…While off-axis illumination and other exposure system based capabilities certainly play a critical role in low k imaging, the challenging nature of extremely low k lithography suggests the game may be won or lost based on proper engineering and analysis of the photomask content. For example, Numerical Technologies [1,2] proposes a path to 65 nm node using a mask intensive "full phase-shifting" methodology while ASML MaskTools is pursuing Chromeless Phase Lithography [3] which also employs a quartz etch in addition to subresolution mask structures. Double Dipole lithography [4] achieves low k imaging through a decomposition and compensation of device layer content into two complementary masks.…”

Design rule optimization of regular layout for leakage reduction in nanoscale design

“…The PS is the critical parameter that highly impact image printability during manufacturing process [8]. Thus minimum and maximum values of the PP is one of the key layout parameter used for optimization as it highly impacts leakage current fluctuation due to NRG.…”

“…Manufacturing aware physical design has been analyzed [7]. The Poly Pitch (PP), Poly End Extension (PEX), Contact Width (CW) and poly contact overlap are recognized as critical parameters that affect manufacturability of standard cells at 65nm technology node [8] and layout restriction to Poly Space (PS) significantly improves manufacturability even under process variations [8]. However, the important effect of NRG has not been incorporated.…”