Lithography-induced limits to scaling of design quality

Abstract

Quality and value of an IC product are functions of power, performance, area, cost and reliability. The forthcoming 2013 ITRS roadmap observes that while manufacturers continue to enable potential Moore's Law scaling of layout densities, the "realizable" scaling in competitive products has for some years been significantly less. In this paper, we consider aspects of the question, "To what extent should this scaling gap be blamed on lithography?" Non-ideal scaling of layout densities has been attributed to (i) layout restrictions associated with multi-patterning technologies (SADP, LELE, LELELE), as well as (ii) various ground rule and layout style choices that stem from misalignment, reliability, variability, device architecture, and electrical performance vs. power constraints. Certain impacts seem obvious, e.g., loss of 2D flexibility and new line-end placement constraints with SADP, or algorithmically intractable layout stitching and mask coloring formulations with LELELE. However, these impacts may well be outweighed by weaknesses in design methodology and tooling. Arguably, the industry has entered a new era in which many new factors -(i) standard-cell library architecture, and layout guardbanding for automated place-and-route; (ii) performance model guardbanding and signoff analyses; (iii) physical design and manufacturing handoff algorithms spanning detailed placement and routing, stitching and RET; and (iv) reliability guardbanding -all contribute, hand in hand with lithography, to a newly-identified "design capability gap". How specific aspects of process and design enablements limit the scaling of design quality is a fundamental question whose answer must guide future R&D investment at the design-manufacturing interface.

Reactive clocks with variability-tracking jitter

“…. µ + 3σ] range of process variability for a particular distribution of dies 3 and the vertical axis represents the cycle period. The bullets represent the delay obtained at the typical corner (TC) and worst-case corner (WC).…”

“…While moving to a new technology node implies a 3-4× increase in manufacturing cost, key metrics such as speed, power, and density are only confined to a 20-20-20% improvement, respectively [3]. The modest progress in performance metrics is largely determined by variability: the increasing gap between worst-case and nominal delays that must be covered by conservative guardband margins.…”

Application of natural linear polysaccharide to green resist polymers for electron beam and extreme-ultraviolet lithography

“…[3][4][5] The work toward the practical use of EUV lithography has been moving forward to pilot manufacturing with a high resolution of less than 10-20 nm for "More Moore" and the development of new technologies for "More-than-Moore". 6,7) In advanced EUV lithography, simultaneous improvement of resist resolution, sensitivity, pattern profile, and line edge roughness (LER) is required in addition to challenges such as higher-power and longer-term reliable EUV source operation. [8][9][10] In particular, in a recent study of the chemical structures of EUV resists, the application of tin oxide films 11) and our efforts to assess metal-oxide-based nanoparticles 12,13) as novel EUV resists were reported.…”