Live together or Die Alone: Block cooperation to extend lifetime of resistive memories

Tavana, Mohammad Khavari; Ziabari, Amir Kavyan; Kaeli, David

doi:10.23919/date.2017.7927153

Cited by 5 publications

(6 citation statements)

References 16 publications

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“…Using single-level (or multi-level) block cooperation, we can increase memory lifetimes by 28% (37%) and 8% (14%), on average, for ECP and Aegis, respectively. This article substantially extends our previous work [47], where we proposed the basic idea of block cooperation, as follows:…”

Section: Introductionsupporting

confidence: 54%

“…Although there are several techniques to evenly distribute the number of writes across all the memory cells, given reliability issues with shrinking technology nodes and the associated manufacturing challenges [51], as well non-uniform write patterns in many applications [38][39][40]47], Fig. 1.…”

Section: Introductionmentioning

confidence: 99%

“…Our characterization uses trace-driven simulation that models the data values transferred between on-chip and main memories. (2) In previous work [47], only statistical simulation is performed to show the benefits of block cooperation. This approach has been followed in previous lifetime studies [16,30,41].…”

Section: Introductionmentioning

confidence: 99%

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Block Cooperation

Tavana

Ziabari

Kaeli

2018

ACM Trans. Archit. Code Optim.

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Block-level cooperation is an endurance management technique that operates on top of error correction mechanisms to extend memory lifetimes. Once an error recovery scheme fails to recover from faults in a data block, the entire physical page associated with that block is disabled and becomes unavailable to the physical address space. To reduce the page waste caused by early block failures, other blocks can be used to support the failed block, working cooperatively to keep it alive and extend the faulty page's lifetime. We combine the proposed technique with existing error recovery schemes, such as Error Correction Pointers (ECP) and Aegis, to increase memory lifetimes. Block cooperation is realized through metadata sharing in ECP, where one data block shares its unused metadata with another data block. When combined with Aegis, block cooperation is realized through reorganizing data layout, where blocks possessing few faults come to the aid of failed blocks, bringing them back from the dead. Our evaluation using Monte Carlo simulation shows that block cooperation at a single level (or multiple levels) on top of ECP and Aegis, boosts memory lifetimes by 28% (37%) and 8% (14%) on average, respectively. Furthermore, using trace-driven benchmark evaluation shows that lifetime boost can reach to 68% (30%) exploiting metadata sharing (or data layout reorganization).

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Section: Introductionsupporting

confidence: 54%

Section: Introductionmentioning

confidence: 99%

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Block Cooperation

Tavana

Ziabari

Kaeli

2018

ACM Trans. Archit. Code Optim.

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“…Table 2 lists the LERs of 512-bit 4LC PCM calculated by Equation (2), for various scrubbing periods and ECC algorithms. 5 2.89 × 10 −1 3.80 × 10 −10 Negligible Negligible 2 6 4.28 × 10 −1 2.64 × 10 −8 Negligible Negligible 2 7 5.65 × 10 −1 7.45 × 10 −7 Negligible Negligible 2 8 7.04 × 10 −1 1.54 × 10 −5 1.27 × 10 −12 Negligible 2 9 8.20 × 10 −1 2.00 × 10 −4 2.32 × 10 −10 Negligible 2 10 9.04 × 10 The SERs of the conventional DRAM-based main memory for personal computers ranges 25,000-75,000 failures in time (FIT) per Mbit, which corresponds to 0.86-2.58 soft errors per hour in a 4-GB DRAM [29]. Converting this value to the error rate of one line, it can be found that the LER should at most 10 −11 to achieve DRAM-compatible reliability.…”

Section: Ser Analysismentioning

confidence: 99%

“…In addition, MLC PCM can be useful for the massive tensor product operations required by deep neural networks (DNN) that utilize different resistive cross-point arrays as synaptic devices, that is, a processing-in-memory (PIM) architecture [3,4]. The superior feature of PCM over other emerging non-volatile memories, such as ReRAM and STT-MRAM, is that MLC technology using a broad resistance spectrum efficiently doubles or triples the storage density and thus makes it possible to meet the increasing demands on the main memory capacity in today's big data era [5,6]. The MLC PCM stores multiple bits in a single cell using the wide variable-resistance characteristic of the GST (Ge 2 Se 2 Te 5 ) material, which changes its physical state when a current pulse is applied.…”

Section: Introductionmentioning

confidence: 99%

Error-Vulnerable Pattern-Aware Binary-to-Ternary Data Mapping for Improving Storage Density of 3LC Phase Change Memory

et al. 2020

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Multi-level cell (MLC) phase-change memory (PCM) is an attractive solution for next-generation memory that is composed of resistance-based nonvolatile devices. MLC PCM is superior to dynamic random-access memory (DRAM) with regard to scalability and leakage power. Therefore, various studies have focused on the feasibility of MLC PCM-based main memory. The key challenges in replacing DRAM with MLC PCM are low reliability, limited lifetime, and long write latency, which are predominantly affected by the most error-vulnerable data pattern. Based on the physical characteristics of the PCM, where the reliability depends on the data pattern, a tri-level-cell (3LC) PCM has significantly higher performance and lifetime than a four-level-cell (4LC) PCM. However, a storage density is limited by binary-to-ternary data mapping. This paper introduces error-vulnerable pattern-aware binary-to-ternary data mapping utilizing 3LC PCM without an error-correction code (ECC) to enhance the storage density. To mitigate the storage density loss caused by the 3LC PCM, a two-way encoding is applied. The performance degradation is minimized through parallel encoding. The experimental results demonstrate that the proposed method improves the storage density by 17.9%. Additionally, the lifetime and performance are enhanced by 36.1% and 38.8%, respectively, compared with those of a 4LC PCM with an ECC.Electronics 2020, 9, 626 2 of 16 MLC PCM as the main memory or a storage class memory (SCM). Indeed, various methods have been introduced to use the MLC technology effectively when targeting PCM as the main memory [7][8][9][10][11][12][13][14][15].For reliable data retention, and for coping with the reduced sensing margin, iterative write-and-verify (read) operations must be executed for each memory cell in the MLC PCM, which deteriorates its lifetime and performance. In addition, MLC PCM suffers from a significantly higher soft error rate (SER) when compared to DRAM. This is mainly caused by the resistance drift phenomenon that blurs the sensing boundary between adjacent states. The use of error-correction code (ECC) is a common technique in reducing the SER of MLC PCM; however, it adversely affects the performance and area efficiency.Scrubbing can help diminish the SER by reading, detecting, and correcting errors by utilizing the parity bit check and writing them back into the cell [16]. The shorter the scrubbing period, the lower the SER. However, frequent scrubbing accelerates the wearing out of PCM. In [10], the authors proposed an efficient scrubbing mechanism that could flexibly determine the scrubbing period considering the error-vulnerable patterns. In addition, recent studies focused on designing reliable 4LC PCM to mitigate the overhead caused by ECC and scrubbing, by expelling the most error-vulnerable pattern [7][8][9][10][11][12].Obviously, long ECC decoding latency is a significant bottleneck in achieving a high-performance memory system [17]. Moreover, complicated ECC algorithms are unacceptable in the MLC PCM based main memory ...

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Cost-effective write disturbance mitigation techniques for advancing PCM density

Tavana¹,

Kaeli²

2017

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Live together or Die Alone: Block cooperation to extend lifetime of resistive memories

Cited by 5 publications

References 16 publications

Block Cooperation

Block Cooperation

Error-Vulnerable Pattern-Aware Binary-to-Ternary Data Mapping for Improving Storage Density of 3LC Phase Change Memory

Cost-effective write disturbance mitigation techniques for advancing PCM density

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