Lizard: Energy-efficient hard fault detection, diagnosis and isolation in the ALU

Abstract

Digital circuits are expected to increasingly suffer from more hard faults due to technology scaling. Especially, a single hard fault in the ALU might lead to a total failure in the embedded systems. In addition, energy efficiency is critical in these systems. To address these increasingly important problems in the ALU, we propose a novel energy-efficient fault-tolerant ALU design called Lizard. Lizard utilizes two 16-bit ALUs to perform 32-bit computations with fault detection and diagnosis. By exploiting predictable operations, fault detection is performed in a single cycle. The 16-bit ALUs can be partitioned into two 8-bit ALUs. When a fault occurs in one of the four 8-bit ALUs, Lizard diagnoses and isolates a faulty 8-bit ALU for itself. After the faulty 8-bit ALU is isolated, Lizard continues its operation using the remaining three 8-bit ALUs, which can detect and isolate another fault. In this way, Lizard can survive faults on at most two sub-ALUs increasing its lifetime and fault tolerance. We conducted comparative evaluations with an unprotected ALU, triple modular redundancy ALU, and quadruple time redundancy ALU in terms of area, energy consumption, performance, and reliability. It is demonstrated that Lizard outperforms other ALU designs in most cases, especially in energy efficiency.

PROCOMON: An Automatically Generated Predictive Control Signal Monitor

“…As the increased hardware cost is usually conflicting with cost constraints existing in many embedded applications, researchers tried to reduce duplication to submodules of the system at the cost of detection coverage. Such implementations concerning redundant or partitioned cores, pipelines, and ALUs have been shown in [2]- [4].…”

Proactively Invalidating Dead Blocks to Enable Fast Writes in STT-MRAM Caches

“…These small values are called narrow-width values. This wellknown characteristic of the applications has been utilized frequently in many prior works for power, performance, and fault-tolerance optimizations [16], [18], [19], [32], [33]. In a narrow-width value, high-order bits (i.e., most significant bits) are all zeros.…”

“…The second optimization technique, called NPW, avoids the redundant write operations to reduce energy consumption further. It is well known that a wide range of applications frequently uses narrow-width values whose upper bits are all zeros [16]- [19]. By exploiting narrowwidth values, NPW avoids unnecessary write operations on some of the STT-MRAM cells if the data stored in the cache entry is narrow-width.…”

A Low-Cost Mechanism Exploiting Narrow-Width Values for Tolerating Hard Faults in ALU

“…Our mechanism is based on the key observation that a large number of ALU operands are narrow-width values of which upper bits are all zeros or ones [4], [5], [6], [7], [12]. In modern processors, the ALU is used to execute arithmetic and logical instructions.…”