LLVM-C2RTL: C/C++ Based System Level RTL Design Framework Using LLVM Compiler Infrastructure

Abstract

As the scale of digital circuit design increases, design and verification using conventional hardware description languages (HDLs), such as verilog-HDL and VHDL, limit efficiency. Consequently, high level synthesis (HLS), as well as domain specific languages (DSLs), which alternates conventional HDLs, are beginning to garner attention. We proposed a design framework that uses the C language as a register transfer level descriptive language. In this study, we introduced a LLVM compiler infrastructure to extend our previous work, support the C/C++ standard as the input code, and aggressively optimize the circuit design. In addition to supporting a single module generation, we extended our framework to support the hierarchical module description for efficient system design. We demonstrated the conversion of the input of C/C++ code into the verilog code, optimize its logic, and construct pipelined logic to achieve the original behavior in multiple clock cycles. Our framework offers a significantly efficient system-level hardware design and a powerful debugging environment with software development platforms and tool-sets. The generated hardware logic performs as well as or better than hand-written logic using conventional HDLs.

Energy-Efficient Implementation of YOLOv8, Instance Segmentation, and Pose Detection on RISC-V SoC

“…In [26], the authors propose a novel method for directly describing the RTL (Register Transfer Level) structure of a pipelined RISC-V processor with cache, memory management unit (MMU), and AXI bus interface using the C++ programming language. This processor C++ model serves as a near cycle-accurate simulation model of the RISC-V core.…”