Load-Balanced Combined Input-Crosspoint Buffered Packet Switches

Rojas‐Cessa, Roberto; Dong, Ziqian

doi:10.1109/tcomm.2011.040111.100256

Cited by 5 publications

(2 citation statements)

References 32 publications

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“…Using this simulation platform, we implement the LB-CQ-FQ switch and some CICQ switches (using different scheduling schemes such as LQF-RR, LB_CICQ-FA [19], and MCBF) for comparison purposes. Each simulated switch is composed of 32 input and 32 output ports.…”

Section: Verification Resultsmentioning

confidence: 99%

A load-balanced crosspoint-queued switch fabric

2013

China Commun.

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The fast growth of Internet has created the need for high-speed switches. Recently, the crosspoint-queue switch has attracted attention because of its scalability and high performance. However, the Crosspoint-Queue switch does not perform well under non-uniform traffic. To overcome this limitation, the Load-Balanced Crosspoint-Queued switch architecture has been proposed. In this architecture, a load-balance stage is placed ahead of the Crosspoint-Queued stage. The load-balance stage transforms the incoming non-uniform traffic into nearly uniform traffic at the input port of the second stage. To avoid out-of-order cells, this stage employs flow-based queues in each crosspoint buffer. Analysis and simulation results reveal that under non-uniform traffic, this new switch architecture achieves a delay performance similar to that of the Output-Queued switch without the need for internal acceleration. In addition, its throughput is much better than that of the pure crosspoint-queued switch. Finally, it can achieve the same packet loss rate as the crosspoint-queue switch, while using a buffer size that is only 65% of that used by the crosspoint-queue switch.

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Section: Verification Resultsmentioning

confidence: 99%

A load-balanced crosspoint-queued switch fabric

2013

China Commun.

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“…The use of these buffers in OMs might make the switch susceptible to out-of-sequence service. To avoid that, OCF is used to select cells, time-stamped at the OMs, from the crosspoint buffers [18].…”

Section: Discussionmentioning

confidence: 99%

Minimizing scheduling complexity with a Clos-network space-space-memory (SSM) packet switch

Lin

Rojas‐Cessa

2013

2013 IEEE 14th International Conference on High Performance Switching and Routing (HPSR)

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In this paper we propose a three-stage space-spacememory (SSM) Clos-network switch that uses crosspoint buffers in the third-stage modules to eliminate the need for performing multiple iterations in for port matching. We show that the proposed switch not only reduces the configuration complexity of space-space-space (S 3 ) switches but also improves switching performance and relaxes configuration timing. We demonstrate these advantages by comparing the performance of the proposed switch using the weighted module-first no-port (WFM-NP) matching scheme to that of a S 3 switch using the original scheduling scheme (with port matching). For higher utilization of the SSM switch, we propose the weighted central-module-link matching (WCMM) scheme. The WCMM scheme rescinds multiple iterations for module matching and yet, it achieves higher performance than the WFM-NP scheme. The advantages of the SSM switch are achieved without memory speedup. The memory addition is a small cost to trade for complexity reduction and performance improvement.

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The optimal joint sequence design in the feedback-based two-stage switch

Huang

2014

Journal of Network and Computer Applications

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Load-Balanced Combined Input-Crosspoint Buffered Packet Switches

Cited by 5 publications

References 32 publications

A load-balanced crosspoint-queued switch fabric

A load-balanced crosspoint-queued switch fabric

Minimizing scheduling complexity with a Clos-network space-space-memory (SSM) packet switch

The optimal joint sequence design in the feedback-based two-stage switch

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