Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers

Ahmed, Nisar; Tehranipoor, Mohammad; Ravikumar, C.P.; Butler, K.M.

doi:10.1109/tcad.2006.884405

Cited by 31 publications

(6 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Figure 3 illustrated the timing waveform of critical signals in Enhanced LCCG for faster-than-at-speed test clock generation. It is known that the global scan enable (GSEN) signal keeps logic high value when the test patterns are scanned into the scan chain [12]. As described in [12], the GSEN signal would switch to logic low value after the last scan-in cycle for supporting both LOC and LOS delay testing Clearly, since C1 and C2 are initialized to logic high values, the test clock TCLK, in which the launch and capture edges are derived from LAUCLK and CAPCLK signals, can then be generated by using OR gate for faster-than-at-speed delay testing.…”

Section: A the Generation Of Faster-than-at-speed Test Clockmentioning

confidence: 99%

Enhanced LCCG: A novel test clock generation scheme for faster-than-at-speed delay testing

Pei

Geng

et al. 2015

The 20th Asia and South Pacific Design Automation Conference

View full text Add to dashboard Cite

On-chip faster-than-at-speed delay testing provides a promising way for small delay defect detection. However, the frequency of on-chip generated test clock would be impacted by process variations. Hence, it requires determining the actual frequency of generated test clock to ensure the effectiveness of faster-than-at-speed delay testing. In this paper, we present a novel test clock generation scheme, namely Enhanced LCCG, for faster-than-at-speed delay testing. In the proposed scheme, faster-than-at-speed test clock is firstly generated by configuring the corresponding control information specified in the test pattern into Enhanced LCCG. Then, by constructing oscillation paths and counting the corresponding oscillation iteration numbers, the actual frequency of test clock can be measured and calculated with high resolution. Experimental results are presented to validate the proposed method.

show abstract

Section: A the Generation Of Faster-than-at-speed Test Clockmentioning

confidence: 99%

Enhanced LCCG: A novel test clock generation scheme for faster-than-at-speed delay testing

Pei

Geng

et al. 2015

The 20th Asia and South Pacific Design Automation Conference

View full text Add to dashboard Cite

show abstract

“…In this paper, the authors proposed a distributed network of cells to drive the scan enable signals at functional speed within local regions of the chip. Overhead costs can be minimized to some extent by pipelining the scan enable signal arriving at these cells [11], however this approach still requires timing closure on the scan enable signal during design. In this case, two different scan enable signals control a flip flop to be run at either LOC or LOS mode.…”

Section: Related Prior Workmentioning

confidence: 99%

Timing Evaluation Tests for Scan Enable Signals with Application to TDF Testing

Zou

Han

Singh

2014

2014 IEEE 23rd Asian Test Symposium

View full text Add to dashboard Cite

Scan based transition delay fault (TDF) tests are generally applied in the launch-on-capture (LOC) mode because the scan enable control signal broadcast to all flip-flops on the die is expensive to implement as a fast switching signal needed to support at-speed launch-on-shift (LOS) tests. However, there is mounting evidence that even when applied at much slower speeds, LOS tests often detect a significant fraction of the timing defects, including many unique failures that are missed by LOC test. This suggests the use of combined LOC and LOS test to increase the TDF coverage beyond that attainable by LOC tests alone. However, to maximize the detection of real delay defects, the LOS tests must be applied at the fastest possible speed (up to the functional clock rate) within the timing limitations of the scan enable. To support such testing, in this paper we present the first test technique to reliably evaluate the switching speed of the scan enable signal. This can vary significantly for individually manufactured instances of the same design due to normal process variations at advanced technology nodes, amplified by near quadratic delays in the long interconnect lengths of this broadcast signal. Once the scan enable speed is determined, LOS tests can be applied at the fastest, most effective speed. Furthermore, the availability of this effective low cost LOS test capability also facilitates the partitioning of the scan flip flops through the use of multiple scan enable signals that apply the delay test in mixed LOS and LOC modes in the different partitions. We show that the use of only two scan enable signals in such an approach can significantly increase TDF test coverage, and raise it very close to the highest possible that is achievable only by enhanced scan.

show abstract

“…Methods to generate fast scan enable signals locally from the global scan enable signal [3], [4] can be used for addressing this issue.…”

Section: Introductionmentioning

confidence: 99%

Generation of Mixed Test Sets for Transition Faults

Pomeranz

2012

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

Test sets that contain both broadside and skewed-load tests are important for achieving the highest possible delay fault coverage for standard-scan circuits. Both types of tests can be represented as , where and are states, and and are primary input vectors. To facilitate the generation of a mixed test set that contains both broadside and skewed-load tests, this paper associates with a property that can be used for estimating whether a skewed-load or a broadside test is more likely to exist with in its second pattern. This paper uses this property for guiding a test generation procedure to consider only one of the two test types for most of the target faults.

show abstract

Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers

Cited by 31 publications

References 17 publications

Enhanced LCCG: A novel test clock generation scheme for faster-than-at-speed delay testing

Enhanced LCCG: A novel test clock generation scheme for faster-than-at-speed delay testing

Timing Evaluation Tests for Scan Enable Signals with Application to TDF Testing

Generation of Mixed Test Sets for Transition Faults

Contact Info

Product

Resources

About