Local Microcode Compaction Techniques

Landskov, David; Davidson, Scott; Shriver, Bruce D.; Mallett, Patrick W.

doi:10.1145/356819.356822

Cited by 220 publications

(53 citation statements)

References 10 publications

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“…Lansdkov et al [27] present a machine model and methods for microcode generation. A subtask of code selection called bundling and a subset of scheduling called compaction are described.…”

Section: Related Workmentioning

confidence: 99%

Global code selection for directed acyclic graphs

Fauth

Hommel

Knoll

et al. 1994

Lecture Notes in Computer Science

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Abstract. We describe a novel technique for code selection based on data-flow graphs, which arise naturally in the domain of digital signal processing. Code selection is the optimized mapping of abstract operations to partial machine instructions. The presented method performs an important task within the retargetable microcode generator CBC, which was designed to cope with the requirements arising in the context of custom digital signal processor (DSP) programming. The algorithm exploits a graph representation in which control-flow is modeled by scopes. IntroductionIn the domain of medium-throughput digital signal processing, micro-programmable processor cores are frequently chosen for system realization. By adding dedicated hardware (accelerator paths), these cores are tailored to the needs of new applications. Optimized processor modules can be reused, which is a major benefit compared to high-level synthesis [28] where a completely new design is developed for each application. Because of the application-specific add-ons and the rather short lifetimes of a specific design, there is a need for retargetable software development tools, especially code-generators. OverviewIn the next section we will shortly discuss several related approaches to code generation and point out some differences of our system. Section 3 introduces the overall architecture and functionality of the CBC code generator. Section 4 explains the code selection task and the basic techniques used. In section 5 our algorithm is presented. We conclude the paper with experimental results. Points of major differences between our code selection approach and similar tasks in "classic" code generation (CG) are: -Complexity of datapaths. CBC has to deal with highly specialized and optimized datapaths. The hardware units make the efficient execution of frequently used operation sequences possible. Operation patterns for the functional units of these datapaths are much more complex than for standard microprocessors.-Type-handling. DSP algorithms may employ a large variety of different word lengths and numerical types. The hardware operators are restricted to fixed word lengths. A correct mapping must always be found. In most CG work this topic is neglected because language definitions (and hence the compilers) are restricted to "implementation-dependent" types. -Evaluation order. Approaches like [6,7] dealing with code selection assume a fixed evaluation order, which is usually derived from the imperative source code. There is no explicit scheduling phase included in the back-ends. Commonly, register allocation is performed during code selection. Most of the time this is done by graph coloring [4] or "on-the-fly".Parallelism of functional blocks. Most DSP architectures contain several functional units that work in parallel. Therefore, the final code cannot be emitted during or immediately after the code selection phase because partial instructions must be "compacted" into complete instructions at a later stage of compilation exploiting the possible para...

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“…Lansdkov et al [27] present a machine model and methods for microcode generation. A subtask of code selection called bundling and a subset of scheduling called compaction are described.…”

Section: Related Workmentioning

confidence: 99%

Global code selection for directed acyclic graphs

Fauth

Hommel

Knoll

et al. 1994

Lecture Notes in Computer Science

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“…Although it was typically referred to as local code compaction-, the similarity to the job of scheduling tasks on processors [108-'117] was soon understood and a number of notions and algorithms from scheduling theory were borrowed by the microprogramming community. Attempts at automating this task have been made since at least the late 1960s [118][119][120][121][122][123][124][125]91,126,127,15]. Since scheduling is known to be NP-complete [115], the initial focus was on defining adequate heuristics [118,128,129,116,130,91].…”

Section: Local Schedulingmentioning

confidence: 99%

Instruction-Level Parallel Processing: History, Overview, and Perspective

Rau

Fisher

1993

Instruction-Level Parallelism

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instruction-level parallelism, VLIW processors, superscalar processors, pipelining, multiple operation issue, speculative execution, scheduling, register allocation Instruction-level Parallelism CILP) is a family of processor and compiler design techniques that speed up execution by causing individual machine operations to execute in parallel. Although ILP has appeared in the highest performance uniprocessors for the past 30 years, the 1980s saw it become a much more significant force in computer design. Several systems were built, and sold commercially, which pushed ILP far beyond where it had been before, both in terms of the amount of ILP offered and in the central role ILP played in the design of the system. By the end of the decade, advanced microprocessor design at all major CPU manufacturers had incorporated ILP, and new techniques for ILP have become a popular topic at academic conferences. This article provides an overview and historical perspective of the field of ILP and its development over the past three decades.

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“…The T set represents the time increments in which the E set is active. Time increments are [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18] JRS arbitrarily defined to be 1 nanosecond per increment. The T set for a MOP thus represents the contiguous time intervals, within the cycle, during which the (i).…”

Section: Jrsmentioning

confidence: 99%

Study and Experimentation of Horizontal Microprocessor Machine Description Techniques

Gieser¹,

Sheraga²

1981

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Local Microcode Compaction Techniques

Cited by 220 publications

References 10 publications

Global code selection for directed acyclic graphs

Global code selection for directed acyclic graphs

Instruction-Level Parallel Processing: History, Overview, and Perspective

Study and Experimentation of Horizontal Microprocessor Machine Description Techniques

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