Local unidirectional bias for smooth cutsize-delay tradeoff in performance-driven bipartitioning

Kahng, Andrew B.; Xu, Xu

doi:10.1145/640015.640019

Cited by 4 publications

(9 citation statements)

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“…More precisely, using "backward edges" of reference [4] does not result in correct calculation of the timing gain for the reason that there is no reduction of the "backward edges" after the v3-move when the topological ordering is from M 0 to M 1 . Furthermore, since the v3-move results in another configuration of "V-shaped nodes" for σ 1 , reference [5] would set the timing gain of this move to zero. In conclusion, to globally reduce the total cut count of all I/O conduits, the timing gain should be calculated as is proposed in our present work.…”

Section: A Timing Gain Function Of a Movementioning

confidence: 99%

“…However, these techniques cannot adequately control the cut count of timing-critical paths in the circuit. Recently, timing-driven partitioning approaches [4][5][6][7][8][9][10][11] have been proposed to simultaneously consider cutsize and the circuit delay. These works may be classified into two categories depending on whether they modify the netlist or not.…”

Section: Introductionmentioning

confidence: 99%

“…However, these methods suffer from choosing the Kmost critical paths since the performance in terms of cutsize, delay and runtime heavily depends on the value of K [9]. A number of researchers [4] [5] have used the signal direction as an indicator of the timing gain function during the move-based partitioning process. Examples include "backward edges" [4] and "V-shaped nodes" [5].…”

Section: Introductionmentioning

confidence: 99%

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PMP: performance-driven multilevel partitioning by aggregating the preferred signal directions of I/O conduits

Hwang¹,

Pedram²

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.

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-In this paper, we present a new performance-driven multilevel partitioning algorithm, which calculates the timing gain of a move in the move-based partitioning strategies based on the aggregation of preferred signal directions. In addition, we propose a new timing-aware multilevel clustering algorithm that uses the connection strength of an edge as the primary objective, and the maximum depth or the maximum hop-count of any path containing the edge as a tiebreaker for the clustering step. These ideas are integrated into a general multilevel partitioning framework, which consists of three phases: uncoarsening, initial partitioning, and coarsening and refinement phases. The benchmarks show that, on average, we can reduce delay by 14.6%, while increasing the cutsize by 1.2% when compared to hMetis[1].

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Section: A Timing Gain Function Of a Movementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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PMP: performance-driven multilevel partitioning by aggregating the preferred signal directions of I/O conduits

Hwang¹,

Pedram²

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.

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“…Circuit delay during placement can be optimized by using buffer insertion, logic replication, or retiming techniques [1][2][3][4]. On the other hand, many techniques [5][6][7][8][9][10][11][12] do not alter the circuit netlist. These techniques often give high weights to or specify physical length constraints for the edges that lie on the critical timing paths of the circuit.…”

Section: Introductionmentioning

confidence: 99%

“…In addition, these techniques tend to over-exert the current set of constraints by making the lengths of the critical nets much shorter than what they have to be in order to satisfy the current timing constraints. A number of researchers [7] [8] have used the signal direction as an indicator of the timing gain function during the move-based partitioning process. Examples include "backward edges" [7] and "V-shaped nodes" [8].These early results motivate the use of signal direction to guide the performance-driven placement process (see also the last paragraph of Section III(A))…”

Section: Introductionmentioning

confidence: 99%

Timing-driven placement based on monotone cell ordering constraints

Hwang¹,

Pedram²

Asia and South Pacific Conference on Design Automation, 2006.

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Abstract− In this paper, we present a new timing-driven placement algorithm, which attempts to minimize zigzags and crisscrosses on the timing-critical paths of a circuit. We observed that most of the paths that cause timing problems in the circuit meander outside the minimum bounding box of the start and end nodes of the path. To limit this undesirable behavior, we impose a physical constraint on the placement problem, i.e., we assign a preferred signal direction to each critical path in the circuit. Starting from an initial placement solution, by using a move-based optimization strategy, these preferred directions force cells to move in a direction that maximizes the monotonic behavior of the timing-critical paths in the new placement solution. To make the direction assignment tractable, we implicitly group all circuit paths into a set of input-output conduits and assign a unique preferred direction to each such conduit. We integrated this idea into a recursive bipartitioning-based placement framework with a min-cut objective function. Experimental results on a set of standard placement benchmarks show that this approach improves the result of a state-of-the-art industrial placement tool for all the benchmark circuits while increasing the wire length by a tolerable amount.

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Exploiting local logic structures to optimize multi-core SoC floorplanning

Sonalkar

Carloni

2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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We present a throughput-driven partitioning and a throughput-preserving merging algorithm for the high-level physical synthesis of latency-insensitive (LI) systems. These two algorithms are integrated along with a published floorplanner [5] in a new iterative physical synthesis flow to optimize system throughput and reduce area occupation. The synthesis flow iterates a floorplanning-partitioning-floorplanning-merging sequence of operations to improve the system topology and the physical locations of cores. The partitioning algorithm performs bottomup clustering of the internal logic of a given IP core to divide it into smaller ones, each of which has no combinational path from input to output and thus is legal for LI-interface encapsulation. Applying this algorithm to cores on critical feedback loops optimizes their length and in turn enables throughput optimization via the subsequent floorplanning. The merging algorithm reduces the number of cores on non-critical loops, lowering the overall area taken by LI interfaces without hurting the system throughput. Experimental results on a large systemon-chip design show a 16.7% speedup in system throughput and a 2.1% reduction in area occupation.

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Local unidirectional bias for smooth cutsize-delay tradeoff in performance-driven bipartitioning

Cited by 4 publications

References 0 publications

PMP: performance-driven multilevel partitioning by aggregating the preferred signal directions of I/O conduits

PMP: performance-driven multilevel partitioning by aggregating the preferred signal directions of I/O conduits

Timing-driven placement based on monotone cell ordering constraints

Exploiting local logic structures to optimize multi-core SoC floorplanning

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