Lock-V: A heterogeneous fault tolerance architecture based on Arm and RISC-V

Marques, Ivo; Rodrigues, Cristiano; Tavares, Adriano; Pinto, Sandro; Gomes, Tiago

doi:10.1016/j.microrel.2021.114120

Cited by 13 publications

(6 citation statements)

References 33 publications

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“…Heterogeneous redundant design is an effective method to improve the fault tolerance against common cause fault. Marques et al proposed a heterogeneous fault-tolerant architecture "Lock-V," which consists of Arm and RISC-V processors deployed on an FPGA, showing that it has an error correction capability for simulated common cause faults [12]. However, complex circuit configurations, such as multiplexing of different processor architectures, are not very desirable in terms of design cost.…”

Section: Related Workmentioning

confidence: 99%

Evaluation of Directive-based Heterogeneous Redundant Design Approaches for Functional Safety Systems on FPGAs

Saikai

Miyata

Manabe

et al. 2022

IJNC

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Field programmable gate arrays (FPGAs) are now used in a wide range of application fields including aerospace, medical, and industrial infrastructure systems, where not only soft errors but also common cause faults must be treated in systems design. Although the heterogeneous redundant design is preferable in such application fields, it tends to be a large burden on system designers. Even with high-level synthesis (HLS) technologies, which have enabled productive design processes without register transfer level (RTL) descriptions, an efficient design approach for redundant design is not always clear. In this paper, we present and evaluates two heterogeneous redundant circuit design approaches for FPGAs: a resource-level approach and strategy-level approach. The resource-level approach focuses on diversity in FPGA technology mapping. For example, two different implementations for a multiplier, one with look-up tables (LUTs) and the other with digital signal processing (DSP) blocks, can form heterogeneous redundancy. The strategylevel approach makes the use of the optimization options offered by an FPGA design tool, called strategies, as a source of diversity. For example, two different implementations can be derived from the same hardware description with area oriented optimization and performance oriented optimization. With both approaches, heterogeneous implementation variants can be generated from the same hardware description code. For evaluation, we implemented homogeneous and heterogeneous redundant designs for proportional-integralderivative (PID) control with those approaches and evaluated their error detection capability and reliability with overclock simulation. The resource-level approach showed that heterogeneous redundant designs by the proposed method have a high error detection rate in both RTL and HLS implementations in an application-level circuit. Although the detection rate of the strategy-level approach was not as high as that of the resource-level one, it was shown to have a certain diversification effect.

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Section: Related Workmentioning

confidence: 99%

Evaluation of Directive-based Heterogeneous Redundant Design Approaches for Functional Safety Systems on FPGAs

Saikai

Miyata

Manabe

et al. 2022

IJNC

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“…The amount of radiation a device can tolerate is indicated as Total Ionizing Dose (TID). Radiation tolerance of a device can be achieved in different ways [41][42][43] and depends on both the design methodology and the technologies used to make them. Examples of devices specifically built to work in space environment include the following:…”

Section: Radiation Hardened Devicesmentioning

confidence: 99%

Oil Spill Identification from SAR Images for Low Power Embedded Systems Using CNN

Diana

Fanucci

2021

Remote Sensing

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Oil spills represent one of the major threats to marine ecosystems. Satellite synthetic-aperture radar (SAR) sensors have been widely used to identify oil spills due to their ability to provide high resolution images during day and night under all weather conditions. In recent years, the use of artificial intelligence (AI) systems, especially convolutional neural networks (CNNs), have led to many important improvements in performing this task. However, most of the previous solutions to this problem have focused on obtaining the best performance under the assumption that there are no constraints on the amount of hardware resources being used. For this reason, the amounts of hardware resources such as memory and power consumption required by previous solutions make them unsuitable for remote embedded systems such as nano and micro-satellites, which usually have very limited hardware capability and very strict limits on power consumption. In this paper, we present a CNN architecture for semantically segmenting SAR images into multiple classes. The proposed CNN is specifically designed to run on remote embedded systems, which have very limited hardware capability and strict limits on power consumption. Even if the performance in terms of results accuracy does not represent a step forward compared with previous solutions, the presented CNN has the important advantage of being able to run on remote embedded systems with limited hardware resources while achieving good performance. The presented CNN is compatible with dedicated hardware accelerators available on the market due to its low memory footprint and small size. It also provides many additional very significant advantages, such as having shorter inference times, requiring shorter training times, and avoiding transmission of irrelevant data. Our goal is to allow embedded low power remote devices such as satellite systems for remote sensing to be able to directly run CNNs on board, so that the amount of data that needs to be transmitted to ground and processed on ground can be substantially reduced, which will be greatly beneficial in significantly reducing the amount of time needed for identification of oil spills from SAR images.

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“…The proposal is based on the lockstep technique by using two processor cores and is capable of recovering from Single Event Upsets (SEU) through partial reconfiguration combined with rollback and roll-forward operations. In [12] the authors propose a heterogeneous fault-tolerant architecture based on Dual-Core Lockstep (DCLS) of different architectures. It combines two different processor architectures: a hardcore processor with ARM architecture and a softcore processor with RISC-V architecture.…”

Section: Introductionmentioning

confidence: 99%