Logarithmic arithmetic as an alternative to floating-point: A review

Chugh, Manik; Parhami, Behrooz

doi:10.1109/acssc.2013.6810472

Cited by 14 publications

(4 citation statements)

References 17 publications

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“…Regarding number format characterization, several works in the literature have considered different emerging number representations (e.g., posit), which face the limitations of mature number formats, like floating-point, especially in new applications, such as those in the machine learning domain. However, most of these efforts are focused on the evaluation and comparison of the code format benefits, as well as the area and power costs of their implementations [35][36][37][38][39][40]. Some works have carried out experiments (in software) to address the implicit resiliency associated with the encoding representation of real numbers [41][42][43].…”

Section: Introductionmentioning

confidence: 99%

Exploring Hardware Fault Impacts on Different Real Number Representations of the Structural Resilience of TCUs in GPUs

Limas Sierra,

Guerrero-Balaguera,

Condia

et al. 2024

Electronics

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The most recent generations of graphics processing units (GPUs) boost the execution of convolutional operations required by machine learning applications by resorting to specialized and efficient in-chip accelerators (Tensor Core Units or TCUs) that operate on matrix multiplication tiles. Unfortunately, modern cutting-edge semiconductor technologies are increasingly prone to hardware defects, and the trend to highly stress TCUs during the execution of safety-critical and high-performance computing (HPC) applications increases the likelihood of TCUs producing different kinds of failures. In fact, the intrinsic resiliency to hardware faults of arithmetic units plays a crucial role in safety-critical applications using GPUs (e.g., in automotive, space, and autonomous robotics). Recently, new arithmetic formats have been proposed, particularly those suited to neural network execution. However, the reliability characterization of TCUs supporting different arithmetic formats was still lacking. In this work, we quantitatively assessed the impact of hardware faults in TCU structures while employing two distinct formats (floating-point and posit) and using two different configurations (16 and 32 bits) to represent real numbers. For the experimental evaluation, we resorted to an architectural description of a TCU core (PyOpenTCU) and performed 120 fault simulation campaigns, injecting around 200,000 faults per campaign and requiring around 32 days of computation. Our results demonstrate that the posit format of TCUs is less affected by faults than the floating-point one (by up to three orders of magnitude for 16 bits and up to twenty orders for 32 bits). We also identified the most sensible fault locations (i.e., those that produce the largest errors), thus paving the way to adopting smart hardening solutions.

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Section: Introductionmentioning

confidence: 99%

Exploring Hardware Fault Impacts on Different Real Number Representations of the Structural Resilience of TCUs in GPUs

Limas Sierra,

Guerrero-Balaguera,

Condia

et al. 2024

Electronics

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“…In particular, the IEEE-754 standard for floating point arithmetic [3] dominated the market for decades. Beyond that, also logarithmic number formats have turned out to be a suitable choice in some special purpose applications, e.g for solving recursive least-squares problems or computing the roots of a polynomial using the Laguerre algorithm [4].…”

Section: Introduction and Related Workmentioning

confidence: 99%

“…4 + 8N 3 − 9N − 9 FLOPs LR-FSD[26] suboptimalComplex LR of H 59.7N 3 FSD ordering of H 10N 4 + 8N 3 − 9N − 9 FLOPs ZF estimate 18N 3 + 6N 2 + N SORN-SD quasi-ML SORN exhaustive Search m N (8N 2 + 4N − 1) SORN OPs Permutation of H 2N m + 0.5N 2 − 1.5N Integer OPs VOLUME 4, 2016 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ This article has been accepted for publication in a future issue of this journal, but has not been fully edited.…”

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confidence: 99%

Hardware Implementation of a Latency-Reduced Sphere Decoder With SORN Preprocessing

et al. 2021

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Unum type-II based Sets-Of-Real-Numbers (SORN) arithmetic is a recently proposed, promising number representation providing fast and low complex implementations of arithmetic operations at the expense of low resolution. The format can be applied for constraining large optimization problems by means of preprocessing. In this work SORN arithmetic is applied for reducing the latency of a Sphere Decoder by excluding a number of solutions in advance. In particular, a comprehensive hardware implementation is presented, consisting of an adapted Sphere Decoder, as well as SORN and matrix preprocessing. Logic and physical synthesis evaluations show that the mean number of visited nodes within the Sphere Decoder can be reduced by up to 76%, resulting in an overall latency reduction of up to 20%. This improvement comes with an area and energy increase of up to 58% and 83%, respectively, compared to a standard Schnorr-Euchner Sphere Decoder.

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“…The range of logarithmic numbers depends on the exponent's integer part, and the precision is defined by its fraction part [1]. Yet, LNS would outperform FLP only if the logarithmic addition and subtraction can be performed with at least the same speed and accuracy as FLP [2].…”

Section: Introductionmentioning

confidence: 99%

RISC Conversions for LNS Arithmetic in Embedded Systems

et al. 2020

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The paper presents an original methodology for the implementation of the Logarithmic Number System (LNS) arithmetic, which uses Reduced Instruction Set Computing (RISC). The core of the proposed method is a newly developed algorithm for conversion between LNS and the floating point (FLP) representations named “looping in sectors”, which brings about reduced memory consumption without a loss of accuracy. The resulting effective RISC conversions use only elementary computer operations without the need to employ multiplication, division, or other functions. Verification of the new concept and related developed algorithms for conversion between the LNS and the FLP representations was realized on Field Programmable Gate Arrays (FPGA), and the conversion accuracy was evaluated via simulation. Using the proposed method, a maximum relative conversion error of less than ±0.001% was achieved with a 22-ns delay and a total of 50 slices of FPGA consumed including memory cells. Promising applications of the proposed method are in embedded systems that are expanding into increasingly demanding applications, such as camera systems, lidars and 2D/3D image processing, neural networks, car control units, autonomous control systems that require more computing power, etc. In embedded systems for real-time control, the developed conversion algorithm can appear in two forms: as RISC conversions or as a simple RISC-based logarithmic addition.

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Logarithmic arithmetic as an alternative to floating-point: A review

Abstract: ABSTRACT:The logarithmic number system (LNS)

Cited by 14 publications

References 17 publications

Exploring Hardware Fault Impacts on Different Real Number Representations of the Structural Resilience of TCUs in GPUs

Exploring Hardware Fault Impacts on Different Real Number Representations of the Structural Resilience of TCUs in GPUs

Hardware Implementation of a Latency-Reduced Sphere Decoder With SORN Preprocessing

RISC Conversions for LNS Arithmetic in Embedded Systems

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