Logic-Based Distributed Routing for NoCs

Abstract

Abstract-The design of scalable and reliable interconnection networks for multicore chips (NoCs) introduces new design constraints like power consumption, area, and ultra low latencies. Although 2D meshes are usually proposed for NoCs, heterogeneous cores, manufacturing defects, hard failures, and chip virtualization may lead to irregular topologies. In this context, efficient routing becomes a challenge. Although switches can be easily configured to support most routing algorithms and topologies by using routing tables, this solution does not scale in terms of latency and area.We propose a new circuit that removes the need for using routing tables. The new mechanism, referred to as Logic-Based Distributed Routing (LBDR), enables the implementation in NoCs of many routing algorithms for most of the practical topologies we might find in the near future in a multicore chip. From an initial topology and routing algorithm, a set of three bits per switch output port is computed. By using a small logic block, LBDR mimics (demonstrated by evaluation) the behavior of routing algorithms implemented with routing tables. This result is achieved both in regular and irregular topologies. Therefore, LBDR removes the need for using routing tables for distributed routing, thus enabling flexible, fast and power-efficient routing in NoCs.

A Scalable and Reconfigurable Fault-Tolerant Distributed Routing Algorithm for NoCs

“…Jie Wu proposes a novel method based on simple dimension order routing (DOR) and odd-even turn model in [22], but it supports fault ring only. Logic-based distributed routing (LBDR) algorithm proposed in [7] gives a new perspective of efficient implementation of NoCs, but it only supports routing of minimum path defined in the original regular mesh topology and can only tolerate fault areas happening at four corners of the mesh structure, like form 'p', 'q', 'd', 'b', and '+' presented in [7]. Here 'p' means fault area happening at the bottom right corner of the mesh structure, and 'q' means fault area happening at the bottom left corner, etc.…”

“…LBDR in [7] only supports corner fault chain and does not provide a mechanism to support boundary fault chain and fault ring. R-DSPIN in [8] can tolerate one fault region located anywhere in the mesh structure, but it does not provide a way of reconfiguration with multiple fault regions.…”

“…For routers in four corner regions, corner RFDR is taken and it behaves the same as LBDR proposed in [7]. Each port of the four output ports only needs three bits: one connection bit and two routing restriction bits, and their values are determined by specific topology and routing restriction sets.…”

“…This is the description of LBDR introduced in [7]. In the proposed boundary RFDR and ring RFDR which will be discussed in Sect.…”

“…However, tables do not scale in terms of latency, power consumption, and area, thus being impractical for NoCs with large number of nodes. Logic-Based Distributed Routing (LBDR) proposed in [7] gives a new perspective of scalable and efficient implementation, but it is limited to some specific topologies that fault nodes can only be located at four corners, or else pairs of end-nodes cannot communicate through a minimal path defined in the original 2D mesh. Reconfigurable Distributed Scalable Predictable Interconnect Network (R-DSPIN) proposed in [8] can support one fault node or be extended to support one fault area no matter where it is located, but it is limited to only one, so when new node fails, the chip may fail, and the re-configurability is greatly reduced.…”