Logic decomposition during technology mapping

Lehman, Eric; Watanabe, Yosinori; Grodstein, J.; Harkness, Heather

doi:10.1109/iccad.1995.480022

Cited by 35 publications

(49 citation statements)

References 14 publications

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“…The approach described by Lehman et al [13] lies between these two extremes: a number of different local algebraic decompositions are encoded into the given subject graph as choices. This leads to less dependence on the original subject graph, but this method suffers from longer run-times.…”

Section: Related Workmentioning

confidence: 99%

Reducing Structural Bias in Technology Mapping

Chatterjee

Mishchenko

Brayton

et al. 2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Technology mapping based on DAG-covering suffers from the problem of structural bias: the structure of the mapped netlist depends strongly on the subject graph. In this paper we present a new mapper aimed at mitigating structural bias. It is based on a simplified cut-based boolean matching algorithm, and using the speed afforded by this simplification we explore two ideas to reduce structural bias. The first, called lossless synthesis, leverages recent advances in structure-based combinational equivalence checking to combine the different networks seen during technology independent synthesis into a single network with choices in a scalable manner. We show how cut-based mapping extends naturally to handle such networks with choices. The second idea is to combine several library gates into a single gate (called a supergate) in order to make the matching process less local. We show how supergates help address the structural bias problem, and how they fit naturally into the cut-based boolean matching scheme. An implementation based on these ideas significantly outperforms state-of-the-art mappers in terms of delay, area and run-time on academic and industrial benchmarks.

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Section: Related Workmentioning

confidence: 99%

Reducing Structural Bias in Technology Mapping

Chatterjee

Mishchenko

Brayton

et al. 2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Therefore the result is largely depending on the preceding decomposition of the network. To get around this problem Lehman [62] combines decomposition with the covering itself. Despite its efficient implementation, exhaustive embedding of the decompositions lead to a significant increase of the size of the subject graph, not practical for sizes of circuits one is typically interested in.…”

Section: Chapter 3 Logic Synthesismentioning

confidence: 99%

“…In [62], a procedure which performs logic decomposition during technology mapping is presented. The data structure used both for the reasoning part, as well as the mapping part is an extended And/Inverter graph.…”

Section: Applicationsmentioning

confidence: 99%

Integrated logic synthesis using simulated annealing

Färm

Dubrova

Kuehlmann

2011

Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI

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KTH School of Information andCommunication Technology SE-164 40 Kista SWEDEN Akademisk avhandling som med tillstånd av Kungl Tekniska högskolan framlägges till offentlig granskning för avläggande av teknologie doktorsexamen i elektronik fredagen den 26 januari 2007 klockan 9.00 i Sal E, Forumhuset, Kungl Tekniska högskolan, Isafjordsgatan 39, Kista. © Petra Färm, januari 2007Tryck: Universitetsservice US AB iii Abstract A conventional logic synthesis flow is composed of three separate phases: technology independent optimization, technology mapping, and technology dependent optimization. A fundamental problem with such a three-phased approach is that the global logic structure is decided during the first phase without any knowledge of the actual technology parameters considered during later phases. Although technology dependent optimization algorithms perform some limited logic restructuring, they cannot recover from fundamental mistakes made during the first phase, which often results in non-satisfiable solutions.We present a global optimization approach combining technology independent optimization steps with technology dependent objectives in an annealing-based framework. We prove that, for the presented move set and selection distribution, detailed balance is satisfied and thus the annealing process asymptotically converges to an optimal solution. Furthermore, we show that the presented approach can smoothly trade-off complex, multiple-dimensional objective functions and achieve competitive results. The combination of technology independent and technology dependent objectives is handled through dynamic weighting. Dynamic weighting reflects the sensitivity of the local graph structures with respect to the actual technology parameters such as gate sizes, delays, and power levels. The results show that, on average, the presented advanced annealing approach can improve the area and delay of circuits optimized using the Boolean optimization technique provided by SIS with 11.2% and 32.5% respectively.Furthermore, we demonstrate how the developed logic synthesis framework can be applied to two emerging technologies, chemically assembled nanotechnology and molecule cascades. New technologies are emerging because a number of physical and economic factors threaten the continued scaling of CMOS devices. Alternatives to silicon VLSI have been proposed, including techniques based on molecular electronics, quantum mechanics, and biological processes. We are hoping that our research in how to apply our developed logic synthesis framework to two of the emerging technologies might provide useful information for other designers moving in this direction.iv

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“…A mapping graph proposed by Lehman et al efficiently encodes multiple AND2/INV networks in a single graph structure [8]. A mapping graph is an AND2/INV network with a new type of node, called choice node.…”

Section: Mapping Graphmentioning

confidence: 99%

An algebraic approach for transistor circuit synthesis

Yoshida

Ikeda

Asada

2005

2005 12th IEEE International Conference on Electronics, Circuits and Systems

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This paper presents an algebraic approach for transistor circuit synthesis. Our approach relies on a graph structure which encodes multiple circuit structural configurations. The proposed procedure implicitly enumerates possible circuit configurations via algebraic transformations in the graph structure, and efficiently finds a minimum solution among them. Experimental results on a benchmark suite targeting standard cell implementations show that the proposed procedure generated smaller transistor circuits than a technology mapping based approach in a comparable runtime.

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Logic decomposition during technology mapping

Cited by 35 publications

References 14 publications

Reducing Structural Bias in Technology Mapping

Reducing Structural Bias in Technology Mapping

Integrated logic synthesis using simulated annealing

An algebraic approach for transistor circuit synthesis

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