Logic-DRAM co-design to efficiently repair stacked DRAM with unused spares

Abstract

Three dimensional (3D) integration is promising to provide dramatic performance and energy efficiency improvement to 3D logic-DRAM integrated computing system, but also poses significant challenge to the yield and reliability. By leveraging logic-DRAM co-design, this paper exploits the cost efficient approach to repair 3D integration induced defective cells in stacked DRAM with unused spares. In particular, we propose to make the DRAM array open its redundancy to off-chip access by small architecture modification, and further design the defective address comparison and redundant address remapping with very efficient architecture on logic die to achieve the equivalent memory repair. Simulation results have demonstrated that the proposed repair technique for DRAM after die stacking is able to significantly alleviate the yield loss, with very low area and power consumption overhead and negligible timing penalty.