Logic-level mapping of high-level faults

Fummi, Franco; Marconcini, C.; Pravadelli, Graziano

doi:10.1016/j.vlsi.2004.07.007

Cited by 13 publications

(6 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Bit coverage has been proved to be related to design errors [8] and unifies into a single metrics the well known metrics concerning statements, branches and conditions coverage. Moreover, bit coverage shows a very high correlation with the traditional gate level stuck-at fault model [11].…”

Section: Functional Atpgmentioning

confidence: 98%

An EFSM-based approach for functional ATPG

Fummi

Marconcini

Pravadelli

2005

Proceedings of the 15th ACM Great Lakes Symposium on VLSI

View full text Add to dashboard Cite

This paper presents an EFSM-based approach for functional automatic test pattern generation (ATPG). It shows how a particular kind of extended FSM (EFSM) can be efficiently traversed by a pseudo-determinist ATPG to control and propagate faults for a functional description of a design. Functional ATPG on such EFSM models have been showed to be more efficient than the ATPG on the original design. However, test sequences generated on such an EFSM can lose their efficacy when simulated on the original description, since they may show some timing discrepancies. To solve this problem, this paper propose a strategy that manipulates the EFSM model.

show abstract

Section: Functional Atpgmentioning

confidence: 98%

An EFSM-based approach for functional ATPG

Fummi

Marconcini

Pravadelli

2005

Proceedings of the 15th ACM Great Lakes Symposium on VLSI

View full text Add to dashboard Cite

show abstract

“…In this paper we rely on the bit coverage fault model, which has been proven to have a good correspondence with gate-level structural faults [8]. In the bit coverage model, faults are injected to every bit of every register in the RTL circuit.…”

Section: Deductive Fault Simulation On Hlddsmentioning

confidence: 99%

“…In this paper, we propose a new approach which is applicable at the Register-Transfer Level (RTL). We build on the bit-coverage fault model, which has proven to have good correspondence with gate-level structural faults [8].…”

Section: Introductionmentioning

confidence: 99%

Register-transfer level deductive fault simulation using decision diagrams

Reinsalu

Raik

Ubar

2010

2010 12th Biennial Baltic Electronics Conference

View full text Add to dashboard Cite

show abstract

“…Some techniques involve a hybrid of these techniques with specialized algorithms such as [4] which uses a strategy to map high-level faults into logic-level faults, genetic [5] and balgebra [6] which provide a more directed approach. Also, techniques in test generation have been proposed with formalize specifications [18].…”

mentioning

confidence: 99%

“…We focus on high abstraction levels of the design at the behavioral level. While [4,5,6] focus on structural errors, they are also targeting the HDL (Hardware Description Language) design at the behavioral level. Our proposed test generation algorithm utilizes high-level scenarios generated directly from the specification to target specification-based errors which are related to the specification utilizing functional validation rather than the relying on the design of the system/DUT to generate the testbench.…”

mentioning

confidence: 99%