Logic minimization and wide fan‐in issues in DPL‐based cryptocircuits against power analysis attacks

Abstract

Summary This paper discusses the use of logic minimization techniques and wide fan‐in primitives and how the design and evaluation of combinational blocks for full‐custom dual‐precharge‐logic‐based cryptocircuits affect security, power consumption, and hardware resources. Generalized procedures for obtaining optimized solutions were developed and applied to the gate‐level design of substitution boxes, widely used in block ciphers, using sense‐amplifier–based logic in a 90‐nm technology. The security of several proposals was evaluated with simulation‐based correlation power analysis attacks, using the secret key measurements to disclosure metric. The simulation results showed increased security‐power‐delay figures for our proposals and, surprisingly, indicated that those solutions which minimized area occupation were both the most secure and the most power‐efficient.