Logic optimization and equivalence checking by implication analysis

Abstract

Abstract-This paper proposes a new approach to multilevel logic optimization based on automatic test pattern generation (ATPG). It shows that an ordinary test generator for single stuckat faults can be used to perform arbitrary transformations in a combinational circuit and discusses how this approach relates to conventional multilevel minimization techniques based on Boolean division. Furthermore, effective heuristics are presented to decide what network manipulations are promising for minimizing the circuit. By identifying indirect implications between signals in the circuit, transformations can be derived which are "good" candidates for the minimization of the circuit. A main advantage of the proposed approach is that it operates directly on the structural netlist description of the circuit so that the technical consequences of the performed transformations can be evaluated in an easy way, permitting better control of the optimization process with respect to the specific goals of the designer. Therefore, the presented technique can serve as a basis for optimization techniques targeting nonconventional design goals. This has already been shown for random pattern testability [11] and low-power consumption [28]. This paper only considers area minimization, and our experimental results show that the method presented is competitive with conventional technologyindependent minimization techniques. For many benchmark circuits, our tool Hannover implication tool based on learning (HANNIBAL) achieves the best minimization results published to date. Furthermore, the optimization approach presented is shown to be useful in formal verification. Experimental results show that our optimization-based verification technique works robustly for practical verification problems on industrial designs.

SPFD-based global rewiring

“…Recently, it has received increased attention due to the need for the interaction between logic synthesis and layout design to solve the timing closure problem. The existing rewiring approaches include the automatic test pattern generation (ATPG) based redundancy addition and removal [2] [5] [6] [7] [12] [14] [15], symmetry detection [4], and the SPFD (Set of Pairs of Functions to be Distinguished) [19][17] based algorithms.…”

SAT-based fault coverage evaluation in the presence of unknown values

“…Indirect implications which are derived during static learning can also be used to increase the accuracy of logic simulation [13,14]. The idea stems from the ATPG domain and is based on evaluating the contrapositive of signals in the circuit.…”

Automating Logic Transformations With Approximate SPFDs

“…This is because the transformation is guaranteed to be valid only under the input space exercised by the given set of input test vectors. In some cases, such as rewiring, a full blown verification may not be required but a faster proof method can be used [4], [29], [30].…”