Logic synthesis for engineering change

Lin, Chia Ching; Chen, Kuang-Chien; Chang, Shih-Chieh; Marek-Sadowska, Malgorzata; Cheng, Kwang-Ting

doi:10.1145/217474.217604

Cited by 72 publications

(39 citation statements)

References 34 publications

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“…, PO m ) at time instance t = t i , the sensitized statements (SSs) of the POs tended to be correct. 1 As a result, the SSs of the POs receive CS points according to the formula of the CS. In short, the CS did not model the masking error situation to estimate the likelihood 1 Otherwise, erroneous values caused by the SSs should make the simulation values of the POs inconsistent with the expected values at t = t i .…”

Section: Motivationmentioning

confidence: 99%

“…These methods can be roughly divided into two categories: 1) symbolic approaches and 2) simulationbased approaches. Symbolic approaches [1]- [6] use a binary decision diagram (BDD) to represent functional manipulation with BDD to formulate the necessary and sufficient condition of fixing design errors. Some recent symbolic works exploit the progress of a Boolean satisfiability (SAT) solver and develops SAT-based approaches [6].…”

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confidence: 99%

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Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging

Jiang

Liu

Jou

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-When hardware description languages (HDLs) are used in describing the behavior of a digital circuit, design errors (or bugs) almost inevitably appear in the HDL code of the circuit. Existing approaches attempt to reduce efforts involved in this debugging process by extracting a reduced set of error candidates. However, the derived set can still contain many error candidates, and finding true design errors among the candidates in the set may still consume much valuable time. A debugging priority method [21] was proposed to speed up the error-searching process in the derived error candidate set. The idea is to display error candidates in an order that corresponds to an individual's degree of suspicion. With this method, error candidates are placed in a rank order based on their probability of being an error. The more likely an error candidate is a design error (or a bug), the higher the rank order that it has. With the displayed rank order, circuit designers should find design errors quicker than with blind searching when searching for design errors among all the derived candidates. However, the currently used confidence score (CS) for deriving the debugging priority has some flaws in estimating the likelihood of correctness of error candidates due to the masking error situation. This reduces the degree of accuracy in establishing a debugging priority. Therefore, the objective of this work is to develop a new probabilistic confidence score (PCS) that takes the masking error situation into consideration in order to provide a more reliable and accurate debugging priority. The experimental results show that our proposed PCS achieves better results in estimating the likelihood of correctness and can indeed suggest a debugging priority with better accuracy, as compared to the CS.Index Terms-Error diagnosis, hardware description language (HDL), HDL code debugging, verification.

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Section: Motivationmentioning

confidence: 99%

mentioning

confidence: 99%

Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging

Jiang

Liu

Jou

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…For example, comparable methods to find resynthesis opportunities in [13,22] are evaluated for at most 5K gates at a time, whereas our techniques typically handle 100K-gate circuits in minutes. Commercial tools often use BDDs but achieve scalability by means of (i) netlist partitioning, and (ii) restricting logic optimization to small windows.…”

Section: Analysis Of Our Approachmentioning

confidence: 99%

SafeResynth: A new technique for physical synthesis

2008

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Physical synthesis is a relatively young field in Electronic Design Automation. Many published optimizations for physical synthesis end up hurting the quality of the final design, often because they neglect important physical aspects of the layout, such as long wires or routing congestion. Our work defines and explores the concept of physical safeness and evaluates empirically its impact on route length, via count and timing. In addition, we propose a new physically safe and logically sound optimization, called SafeResynth, which provides immediately-measurable improvements without altering the design's functionality. SafeResynth can enhance circuit timing without detrimental effects on route length and congestion. We achieve these improvements by performing a series of netlist transformations and re-placements that are individually evaluated for logical soundness (that is, they do not alter the logic functionality) and for physical safeness. When used alone, SafeResynth improves circuit delay of IWLS'05 benchmarks by 11% on average after routing, while increasing route length by less than 0.2%. Since transistors are not affected by SafeResynth, it can also be applied to post-silicon debugging, where only metal fixes are possible. 1

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“…In the case of engineering changes (EC) [3], a logic netlist is modified to reflect specification changes at a higher level of abstraction. Logic transformations are also important during rewiring-based postsynthesis performance optimization [4], [5], where designs are optimized at particular internal locations to meet specification constraints.…”

Section: Introductionmentioning

confidence: 99%

Automating Logic Transformations With Approximate SPFDs

Yang

Sinha

Veneris

et al. 2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-During the VLSI design process, a synthesized design is often required to be modified in order to accommodate different goals. To preserve the engineering effort already invested, designers seek small logic structural transformations to achieve these logic restructuring goals. This paper proposes a systematic methodology to devise such transformations automatically. It first presents a simulation-based formulation to approximate SPFDs and avoid the memory/time explosion issue inherent with the original representation. Then it uses this new data structure to devise the required transformations dynamically without the need of a static dictionary model. The methodology is applied to both combinational and sequential designs with transformations at a single or multiple locations. An extensive suite of experiments documents the benefits of the proposed methodology when compared to existing practices.

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Logic synthesis for engineering change

Cited by 72 publications

References 34 publications

Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging

Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging

SafeResynth: A new technique for physical synthesis

Automating Logic Transformations With Approximate SPFDs

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