LogTOTEM: A Logarithmic Neural Processor and its Implementation on an FPGA Fabric

Abstract

This paper describes the design of a neural network architecture optimised for use with the Reactive Tabu Search (RTS) training algorithm. The neural network is built using the hybrid-Logarithmic Number System (hybrid-LNS) instead of the traditional fixed-point methods for the multiplyaccumulate (MAC) unit contained in each neuron. The circuits have been designed and implemented using between 4 and 8 bits of fractional precision for the logarithmic representation of the weights and the data. The architecture is based on the existing TOTEM VLSI chip and contains 32 neurons each having a 256 x 10-bit weight RAM. The device has been implemented on a Virtex XCV600 device where it consumed less 6025 slices with 4 bits of fractional precision of the logarithms and 6280 slices with 5 bits of fractional precision. At 4-bits This represents a (45%) reduction in logic resources required by the neuron array and an overall reduction of 10% of the FPGA resources when compared to the SoftTOTEM device built using the same technology.

Hardware architecture for a bidirectional hetero-associative Protein Processing Associative Memory

“…Although, many architectures exist that attempt solutions for problems in this domain (Toffoli, 1984;Amaral and Ghosh, 1994;Lee et al, 2006;Teich, 2008;Anzellotti et al, 1995;Lee et al, 2007), these are based on Arithmetic and Logic Units (ALUs) and often are simply Von Neumann style processors in parallel, and suffer from the well known Von Neumann bottleneck. To avoid going into the realms of philosophy, an AI application may simply be defined as one that tries to achieve behaviour that will be displayed by intelligent beings (like humans).…”