Long-term drift of Si-MOS quantum dots with intentional donor implants

Abstract

Charge noise can be detrimental to the operation of quantum dot (QD) based semiconductor qubits. We study the low-frequency charge noise by charge offset drift measurements for Si-MOS devices with intentionally implanted donors near the QDs. We show that the MOS system exhibits non-equilibrium drift characteristics, in the form of transients and discrete jumps, that are not dependent on the properties of the donor implants. The equilibrium charge noise indicates a 1/ f noise dependence, and a noise strength as low as , comparable to that reported in more model GaAs and Si/SiGe systems (which have also not been implanted). We demonstrate that implanted qubits, therefore, can be fabricated without detrimental effects on long-term drift or 1/ f noise for devices with less than 50 implanted donors near the qubit.

Effect of device design on charge offset drift in Si/SiO2 single electron devices

“…29 (It should be noted that these single layer devices often become more stable at longer times. 36 ) Second, the data show isolated discrete jumps or drifts, which are not stationary. Third, the device shows some stable periods where Q 0 ( t ) takes on a value within a stationary band.…”

“…The charge offset drift Q 0 ( t ) has three distinct features, which were also observed in devices of the same design fabricated at Sandia National Labs. 36 First, over the course of the first two days, Q 0 ( t ) shows an evolution from rapid drift toward slower drift while winding Q 0 ( t ) through several e . This phenomenon has been previously referred to as transient relaxation.…”

“…Workers at Sandia National Laboratories and the University of Sherbrook have pioneered fabrication of Si/SiO 2 -based SEDs with a single layer of doped polysilicon gates. 35,36 Those devices present an opportunity to assess the robustness of the above explanation for Q 0 ( t ) because they do not have a blanket gate to function as an SED, and their Q 0 ( t ) behavior differs from the mesa-etched SOI devices while not altering the Si/SiO 2 material system. 36 In this manuscript, we present data showing that Si/SiO 2 single gate layer devices show significantly larger Δ Q 0 than their SOI counterparts and, moreover, that Δ Q 0 can be reduced with the addition of another gate covering the fine area of the device.…”

Exploiting a Single‐Crystal Environment to Minimize the Charge Noise on Qubits in Silicon

“…For silicon gate‐defined quantum dots, the dominant source of charge noise is known to originate from within the oxide dielectric that separates the quantum wells from the electrostatic gates, and/or near the interface between the semiconductor and the dielectric. [ 20–24 ] More specifically, Si‐MOS qubits are exposed to an amorphous Si/SiO 2 interface while SiGe devices have Si/SiGe heterointerfaces in very close proximity to the quantum well with an additional Si/Al 2 O 3 interface nearby. [ 20–23 ] Ongoing efforts in device fabrication are aimed at improving the quality of these interfaces.…”

“…[ 20–23 ] Ongoing efforts in device fabrication are aimed at improving the quality of these interfaces. Improving interface quality, however, provides a challenging optimization problem with the charge noise magnitude depending on many parameters including wafer type, [ 23 ] lithographic gate design, [ 24 ] interfacial disorder, [ 25 ] and oxide thickness. [ 22 ] In this work, we show that the effect of these surface or interface defects, that give rise to charge noise, can be significantly reduced by fabricating crystalline qubits that are remote from surfaces and interfaces.…”