Longevity of Commodity DRAMs in Harsh Environments Through Thermoelectric Cooling

Abstract

Today, more and more commodity hardware devices are used in safety-critical applications, such as advanced driver assistance systems in automotive. These applications demand very high reliability of electronic components even in adverse environmental conditions, such as high temperatures. Ensuring the reliability of microelectronic components is a major challenge at these high temperatures. The computing systems of these applications rely on DRAMs as working memory, which are built upon bit cells that store charges in capacitors. These commodity DRAMs are optimized for cost per bit and not for high reliability. Thus, very high temperatures impose an enormous challenge for commodity DRAMs as the data retention time and reliability decrease largely, affecting the data correctness. Data correctness can be ensured up to certain temperatures by increasing the refresh rate to counterbalance the retention time reduction. However, this severely degrades the access latencies and the usable DRAM bandwidth. To overcome these limitations, we present for the first time a Thermoelectric Cooling (TEC) solution for commodity DRAMs in harsh-environments, such as automotive. Our TEC solution enables the use of commodity off-the-shelf DRAMs in safety-critical applications by reducing the temperature conditions to a range where they can operate reliably. This TEC solution is applied a posteriori to the DRAM chips without using high-cost package solutions. Thus, it maintains the low-cost targets of such devices, improves the reliability, and at the same time, counterbalances the adverse effects of increasing the refresh rate. To quantitatively evaluate the benefits of TEC on commodity DRAMs in harsh-environments, we performed system-level evaluations with several applications backed up by the measured data on commodity DRAMs. Our experimental results, using accurate multi-physics simulations that employ finite element method, demonstrate that the TECbased cooling ensures that the maximum temperature of all DRAM chips is always below 85°C despite that the original on-chip temperature (i.e., in the absence of our TEC based cooling) goes beyond 120°C.

Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics

“…For example, a coarse-grained approach such as page retirement [49,60,83,84,88,103] efficiently mitigates a small number 9 These mechanisms commonly fall under the umbrella of memory reliability, availability and serviceability (RAS) features [312][313][314]. 10 Consumers with exceptional reliability needs, such as those targeting extreme or hostile environments (e.g., military, automotive, industrial, extraterrestrial), may take more extreme measures (e.g., custom components [158, 159,[334][335][336][337][338][339][340], redundant resources [93,341,342]) to ensure that memory errors do not compromise their systems. 11 Academic works speculate that commodity DRAM targets a bit error rate (BER) within the range of 10 −16 − 10 −12 [86,92,321,343], but we are not aware of industry-provided values.…”

Architectural evaluation of programmable transistor-based capacitorless DRAM for high-speed system-on-chip applications

“…In realistic applications of systems supporting advanced computations, the temperature can rise even above 100 °C due to extensive data processing and working environments. 33) Therefore, the reliability of both architecture's high-temperature applications (up to 125 °C) needs to be ascertained. At higher temperatures, higher recombination and generation rates degrade states 1 and 0, respectively, which results in a significant degradation in hole concentration over time.…”

Radiation‐Tolerant Electronic Devices Using Wide Bandgap Semiconductors

“…The read‐out current in Figure 20h indicates the three negative current spikes these three times as the gate leakage current and SEE‐induced electrons are generated in the gate insulator through gate voltage. [ 238 ] Variation of the drain current with LET is checked since the current for a “0” is greater than the current for a “1”. A soft error is induced in the device, which further illustrates that HEPs can generate a large number of e–h pairs and change the information in cells.…”

“…The associate sensitivity increases with the increasing gate length. [239] Yan et al recently reported the SEEs in 1T-DRAM based on indium gallium arsenide on insulator (InGaAs-OI) transistor with high energy proton (HEP) [238] (Figure 20d-i). The HEP ranging from 10 to 100 MeV.cm 2 mg −1 strikes perpendicularly to the channel in different positions, as shown in Figure 20d.…”

“…i) Time history of the drain current characteristic under radiation damage. Reproduced with permission [238]. Copyright 2021, IEEE.…”