Loopback architecture for wafer-level at-speed testing of embedded HyperTransport&lt;sup&gt;TM&lt;/sup&gt; processor links

Loke, Alvin L. S.; Doyle, B.S.; Oshima, Michael M.; Williams, Wade L.; Lewis, Robert W.; Wang, Charles L.; Hanpachern, Audie; Tucker, Karen; Gurunath, Prashanth; Asada, G.; Lackey, Chad O.; Wee, Tin Tin; Fang, Emerson S.

doi:10.1109/cicc.2009.5280778

Cited by 8 publications

(1 citation statement)

References 4 publications

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“…Forwarded-clock links (FC) have been widely applied in the high-density multi-lane processor's interfaces, such as Quick-Path Interconnect and HyperTransport [1][2]. As the chip-to-chip bandwidth is increasing aggressively to satisfy the demands of the multi-core system performance, the power dissipation of these high-speed FC transceivers has become a major concern [3][4].…”

Section: Introductionmentioning

confidence: 99%

A 1.2 pJ/b 6.4 Gb/s 8+1-lane forwarded-clock receiver with PVT-variation-tolerant all-digital clock and data recovery in 28nm CMOS

Shuai

Liu

et al. 2013

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference

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This paper presents an energy/area-efficient forwardedclock receiver fabricated in a 28nm CMOS process. The receiver consists of 8 data lanes plus one forwarded-clock lane, and adopts a novel all-digital clock and data recovery (CDR) using a delaylocked loop (DLL). The all-digital DLL with calibration can generate accurate multiphase clocks for both duty-cycle correction and the data recovery in the presence of process variations. The all-digital DLL-based CDR can enter into openloop mode after lock-in to reduce power and eliminate the clock dithering phenomenon. Furthermore, the CDR can re-lock in the closed-loop mode using a proposed update algorithm to track the temperature and voltage variations without disturbing the data recovery. Measurement results show that the receiver can operate at a data rate of 6.4 Gb/s with a BER<10 -12 , consuming 7.5 mW per lane under a 0.85 V power supply. The core receiver occupies an area of 0.02 mm 2 per lane.

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Section: Introductionmentioning

confidence: 99%

A 1.2 pJ/b 6.4 Gb/s 8+1-lane forwarded-clock receiver with PVT-variation-tolerant all-digital clock and data recovery in 28nm CMOS

Shuai

Liu

et al. 2013

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference

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Extending HyperTransport™ technology to 8.0 Gb/s in 32-nm SOI-CMOS processors

Doyle

Loke

Maheshwari

et al. 2011

IEEE Asian Solid-State Circuits Conference 2011

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An Embedded All-Digital Circuit to Measure PLL Response

Fischette

Loke

Desantis

et al. 2010

IEEE J. Solid-State Circuits

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Loopback architecture for wafer-level at-speed testing of embedded HyperTransport<sup>TM</sup> processor links

Cited by 8 publications

References 4 publications

A 1.2 pJ/b 6.4 Gb/s 8+1-lane forwarded-clock receiver with PVT-variation-tolerant all-digital clock and data recovery in 28nm CMOS

A 1.2 pJ/b 6.4 Gb/s 8+1-lane forwarded-clock receiver with PVT-variation-tolerant all-digital clock and data recovery in 28nm CMOS

Extending HyperTransport™ technology to 8.0 Gb/s in 32-nm SOI-CMOS processors

An Embedded All-Digital Circuit to Measure PLL Response

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Loopback architecture for wafer-level at-speed testing of embedded HyperTransport<sup>TM</sup> processor links

Cited by 8 publications

References 4 publications

A 1.2 pJ/b 6.4 Gb/s 8&#x002B;1-lane forwarded-clock receiver with PVT-variation-tolerant all-digital clock and data recovery in 28nm CMOS

A 1.2 pJ/b 6.4 Gb/s 8&#x002B;1-lane forwarded-clock receiver with PVT-variation-tolerant all-digital clock and data recovery in 28nm CMOS

Extending HyperTransport&#x2122; technology to 8.0 Gb/s in 32-nm SOI-CMOS processors

An Embedded All-Digital Circuit to Measure PLL Response

Contact Info

Product

Resources

About

A 1.2 pJ/b 6.4 Gb/s 8+1-lane forwarded-clock receiver with PVT-variation-tolerant all-digital clock and data recovery in 28nm CMOS

A 1.2 pJ/b 6.4 Gb/s 8+1-lane forwarded-clock receiver with PVT-variation-tolerant all-digital clock and data recovery in 28nm CMOS

Extending HyperTransport™ technology to 8.0 Gb/s in 32-nm SOI-CMOS processors