Lossless Compression Algorithms for Post-OPC IC Layout

Abstract

An important step in today's Integrated Circuit (IC) manufacturing is optical proximity correction (OPC). While OPC increases the fidelity of pattern transfer to the wafer, it also results in significant increase in IC layout file size. In this paper, we develop two techniques for compressing post-OPC layout data while remaining compliant with existing industry standard data formats such as OASIS and GDSII. The motivation for doing so is for the resulting compressed files to be viewed and edited by any industry standard CAD tools without a decoder. Our approach is to eliminate redundancies in the representation of the geometric data by finding repeating groups of polygons between multiple cells as well as within a cell. We refer to the former as "inter-cell sub-cell detection" and the later as "intra-cell sub-cell detection". Both problems are NP hard, and as such, we propose two sets of greedy algorithms to solve them. We show the results of our proposed inter-cell and intra-cell algorithms on actual 90nm, 130nm, and 180nm IC layouts.