LOTTERYBUS: a new high-performance communication architecture for system-on-chip designs

Abstract

This paper presents LOTTERYBUS, a novel high-performance communication architecture for system-on-chip (SoC) designs. The LOTTERYBUS architecture was designed to address the following limitations of current communication architectures: (i) lack of control over the allocation of communication bandwidth to different system components or data flows (e.g., in static priority based shared buses), leading to starvation of lower priority components in some situations, and (ii) significant latencies resulting from variations in the time-profile of the communication requests (e.g., in time division multiplexed access (TDMA) based architectures), sometimes leading to larger latencies for high-priority communications.We present two variations of LOTTERYBUS: the first is a low overhead architecture with statically configured parameters, while the second variant is a more sophisticated architecture, in which values of the architectural parameters are allowed to vary dynamically.Our experiments investigate the performance of the LOTTERY-BUS architecture across a wide range of communication traffic characteristics. In addition, we also analyze its performance in a 4x4 ATM switch sub-system design. The results demonstrate that the LOTTERYBUS architecture is (i) capable of providing the designer with fine grained control over the bandwidth allocated to each SoC component or data flow, and (ii) well suited to provide high priority communication traffic with low latencies (we observed upto 85.4% reduction in communication latencies over conventional onchip communication architectures).

Design and implementation of a fair credit-based bandwidth sharing scheme for buses

“…Other policies such as lottery [17] and random permutations [13] have been shown to be also compatible with probabilistic timing analysis and, in particular, with MBPTA. Those policies assign the grant randomly with different constraints with the aim of making the worst case being closer to the average case and thus, improving WCET estimates.…”

“…Several arbitration policies have been proposed to control the access to the shared bus and other resources. Among those, we find round-robin, FIFO, TDMA, lottery, and random permutations [12], [13], [15], [17]. All those policies have been shown to provide a high degree of fairness across cores in terms of number of requests (slots) granted.…”

On-Chip Bus Arbiter Testing and Verification in FPGA

“…Using Vivado design suite we calculated total delay in these logic circuits we get 147.32 ns for RRA.The performance of any arbiter is determined based on the waiting time or latency, fairness to access the bus [5]. Here we described that the experimental setup environment of the decision maker logics that is arbiter component.…”

Smart Bus Arbiter for QoS control in H.264 decoders

“…The AHB arbiter can have various arbitration policies such as fixed priority [7], Round-Robin [8], TDMA [9], and Lottery [10]. The TDMA and the Lottery scheme can allocate weighted chances of arbitration to certain masters.…”