Low area and high speed SHA-1 implementation

Jung, Eun-Gu; Han, Demin; Lee, Jeong-Gun

doi:10.1109/isocc.2011.6138786

Cited by 4 publications

(3 citation statements)

References 7 publications

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“…A detailed study has been carried out on the existing hardware designs of MISTY1, KASUMI, AES, SHA-1, CAMELLIA and SAFER [5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22]. The review covered the comparison of performance parameters i.e.…”

Section: Introductionmentioning

confidence: 99%

“…In comparison to high throughput encryption cores, compact designs make use of the logic optimization techniques for transformation functions and s-boxes using combinational logic [5][6][7][8][9][10], [12][13][14][15][16][17][18], [21], [22]. Besides, re-utilization methodologies have also been implemented exploiting the rolling-feature of the architecture.…”

Section: Introductionmentioning

confidence: 99%

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Area-Efficient Hardware Architectures of MISTY1 Block Cipher

Yasir¹,

Wu²,

Chen³

et al. 2018

RADIOENGINEERING

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In this paper, state-of-the-art hardware implementations of MISTY1 block cipher are presented for areaconstrained wireless applications. The proposed MISTY1 architectures are characterized of highly optimized transformation functions i.e. FL and {FO-XOR-EKG}. The FL function re-utilizes logic AND-OR-XOR combinations whereas {FO-XOR-EKG} function explores 2 × compact design schemes for s-boxes implementation. A Combined Substitution Unit (CSU) and threshold area implementation are proposed for s-boxes based on Boolean reductions and Common Sub-expression Eliminations (CSEs). Besides, {FO-XOR-EKG} function is designed for manifold operations of FO / FI functions, 32-bit XOR operation and extended key generation thereby reducing the area. Hardware implementations on ASIC 180nm, 1.8V standard library cell realized compact and threshold MISTY1 designs constituting 1853 and 1546 NAND gates with throughput values of 41.6 Mbps and 4.72 Mbps respectively. A comprehensive comparison with existing cryptographic hardware designs establishes that the proposed MISTY1 architectures are the most area-efficient implementations till date.

show abstract

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Area-Efficient Hardware Architectures of MISTY1 Block Cipher

Yasir¹,

Wu²,

Chen³

et al. 2018

RADIOENGINEERING

View full text Add to dashboard Cite

show abstract

“…1. For high-throughput SHA-1 design, the techniques such as loop unfolding, pre-processing [2,3], multi-input adding based on a carry-save adder [4] and pipelining [5] have been proposed. In this paper, design methods that loop unfolding, preprocessing and pipelining were used.…”

Section: Introductionmentioning

confidence: 99%

Design for high throughput SHA-1 hash function on FPGA

Kim

Lee

Won

2012

2012 Fourth International Conference on Ubiquitous and Future Networks (ICUFN)

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In this paper, we propose SHA-1 architectures to achieve high-throughput hardware implementations. Two techniques such as loop unfolding and pre-processing were used for high-speed SHA-1 core design. The system is made of four sub-modules to increase throughput. Xilinx Virtex-6 FPGA is used for implementation. Implemented SHA-1 module achieves a throughput of 7.35 Gbps, and its behavior has been verified by connecting with Xilinx MicroBlaze soft processor.

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A High Speed SM3 Algorithm Implementation for Security Chip

Zang

Zhao

et al. 2021

2021 IEEE 5th Advanced Information Technology, Electronic and Automation Control Conference (IAEAC)

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Low area and high speed SHA-1 implementation

Cited by 4 publications

References 7 publications

Area-Efficient Hardware Architectures of MISTY1 Block Cipher

Area-Efficient Hardware Architectures of MISTY1 Block Cipher

Design for high throughput SHA-1 hash function on FPGA

A High Speed SM3 Algorithm Implementation for Security Chip

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