Low-area scalable hardware architecture for DMM-1 encoder of 3D-HEVC video coding standard

Abstract

This work presents a low-area scalable architecture for the Depth Modelling Mode 1 (DMM-1) encoder of the 3D High Efficiency Video Coding (3D-HEVC) standard, removing the refinement stage. This simplification causes a small BD-rate increase (0.09%) but a significant reduction in memory usage of 30%. The scalable architecture can support different block sizes. Synthesis results for ST 65 nm Standard Cells technology show that the designed structure is capable of reaching real-time processing of HD 1080 p videos for all block sizes.

Hardware-Oriented Wedgelet Evaluation Skip for DMM-1 in 3D-HEVC

“…Different values of N can be used when applying the proposed algorithm according to the system specification; e.g., for a system that requires lower encoding effort, N can be reduced and for a system that requires better BD-rate N can be increased. Moreover, considering that the hardware designed for DMM-1 in the literature are pattern-based [11]- [13], the proposed solution in this paper is more feasible for a real-time hardware implementation compared against the line-based GMOFs variations.…”

“…Moreover, these algorithms have a high difficult to be implemented in hardware because the line-based approach requires floating point number, increasing the complexity when designing a hardware. Allied to it, the hardware designs found in the literature [11]- [13] that allows encoding DMM-1 in real-time, requires a considerable high area, power dissipation, and/or Bjontegaard Delta-Rate impact (BD-rate) [14].…”

High Efficient Architecture for 3D-HEVC DMM-1 Decoder Targeting 1080p Videos

“…Sanchez et al [8] and Amish et al [9] designed a DMMs architecture for the encoding process. A DMM-4 encoder architecture was designed in [10] and a DMM-1 encoder architecture was designed in [11]. Afonso et al [12] designed an encoder architecture for DIS.…”