Low-complexity decoding for non-binary LDPC codes in high order fields

Voicila, Adrian; Declercq, David; Verdier, François; Fossorier, M.P.C.; Urard, Pascal

doi:10.1109/tcomm.2010.05.070096

Cited by 199 publications

(154 citation statements)

References 17 publications

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“…More recently, an implementation based on the fast Fourier transform [2] was shown to reduce the complexity to Ø(q log q). Beyond that, a variety of simple but sub-optimal decoding algorithms have been proposed in the literature, such as the extended min-sum (EMS) algorithm [3] and the trellisbased EMS algorithm [4]. For computing iterative BP decoding thresholds, a q-ary extrinsic information transfer (EXIT) analysis was proposed in [5] and was later developed into a version suitable for protograph-based code ensembles in [6].…”

Section: Index Termsmentioning

confidence: 99%

Design of Spatially Coupled LDPC Codes Over GF $(q)$ for Windowed Decoding

Wei

Mitchell

Fuja

et al. 2016

IEEE Trans. Inform. Theory

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In this paper we consider the generalization of binary spatially coupled low-density parity-check (SC-LDPC) codes to finite fields GF(q), q ≥ 2, and develop design rules for q-ary SC-LDPC code ensembles based on their iterative belief propagation (BP) decoding thresholds, with particular emphasis on low-latency windowed decoding (WD). We consider transmission over both the binary erasure channel (BEC) and the binary-input additive white Gaussian noise channel (BIAWGNC) and present results for a variety of (J, K)-regular SC-LDPC code ensembles constructed over GF(q) using protographs.Thresholds are calculated using protograph versions of q-ary density evolution (for the BEC) and qary extrinsic information transfer analysis (for the BIAWGNC). We show that WD of q-ary SC-LDPC codes provides significant threshold gains compared to corresponding (uncoupled) q-ary LDPC block code (LDPC-BC) ensembles when the window size W is large enough and that these gains increase as the finite field size q = 2 m increases. Moreover, we demonstrate that the new design rules provide WD thresholds that are close to capacity, even when both m and W are relatively small (thereby reducing decoding complexity and latency). The analysis further shows that, compared to standard flooding-schedule decoding, WD of q-ary SC-LDPC code ensembles results in significant reductions in both decoding complexity and decoding latency, and that these reductions increase as m increases.For applications with a near-threshold performance requirement and a constraint on decoding latency, we show that using q-ary SC-LDPC code ensembles, with moderate q > 2, instead of their binary counterparts results in reduced decoding complexity.

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Section: Index Termsmentioning

confidence: 99%

Design of Spatially Coupled LDPC Codes Over GF $(q)$ for Windowed Decoding

Wei

Mitchell

Fuja

et al. 2016

IEEE Trans. Inform. Theory

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“…In [4], the forward-backward (F-B) architecture is proposed for EMS algorithm implementation, in this method, a check node message update is based on several similar elementary check units (ECUs) to reduce computation complexity. But each ECU just processes two symbols per system cycle, which means 3ðd c À 2Þ ECU computations are needed for one (check node CN to variable node VN) C2V update.…”

Section: Introductionmentioning

confidence: 99%

High throughput and low complexity implementation of NB-LDPC decoder based on EMS algorithm

long

Lin

2016

IEICE Electron. Express

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Non-Binary Low-Density-Parity-Check codes (NB-LDPC) have shown superior performance but its huge complexity and low throughput prevent it from practical applications. This paper presents a novel architecture to implement a kind of high-throughput low-complexity irregular quasicyclic NB-LDPC decoder over GF (16) based on Extended Min-Sum (EMS) Algorithm. Double clocks are adopted in this paper. The low frequency clock at 60 MHz serves as the system clock and the high frequency clock at 480 MHz works for check nodes and variable nodes thus they can be reused 8 times during one system clock period as a result the complexity can be largely reduced. Synthesis result shows that the throughput can achieve 68.57 Mbps at 5 iterations. FPGA testing result shows that the decoder has little performance degradation compared with its floating model and it can provide about 0.5 dB coding gain compared with its binary LDPC code of the same block length. The proposed architecture can be conveniently extended to higher Galois Filed such as GF (64) or GF (256) and it can be applied for different code length and rate by modifying a slight part of the decoder. Compared with previous works, the decoder proposed in this paper is more efficient for practical applications.

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“…The work from [42] exchanges a full set of messages which turns into a higher number of bits at the CN output. As can be seen, proposals from [52,44,24] eliminate the q-dependence, exchanging only a fraction n m < q of the reliabilities. This proposals maintain a strong dependence on the CN degree d c , which penalizes for high-rate NB-LDPC codes.…”

Section: Proposalmentioning

confidence: 98%

“…We consider the same number of quantization bits for all proposals (w = 6 bits) and we set n m = 16 and n v = 5 according to [52,44,24,23] as they propose for their codes. The work from [42] exchanges a full set of messages which turns into a higher number of bits at the CN output.…”

Section: Proposalmentioning

confidence: 99%

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VLSI algorithms and architectures for non-binary-LDPC decoding

Lacruz¹,

Jesús²

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This thesis studies the design of low-complexity soft-decision Non-Binary LowDensity Parity-Check (NB-LDPC) decoding algorithms and their corresponding hardware architectures suitable for decoding high-rate codes at high throughput (hundreds of Mbps and Gbps).In the first part of the thesis the main aspects concerning to the NB-LDPC codes are analyzed, including a study of the main bottlenecks of conventional softdecision decoding algorithms (Q-ary Sum of Products (QSPA), Extended MinSum (EMS), Min-Max and Trellis-Extended Min-Sum (T-EMS)) and their corresponding hardware architectures. Despite the limitations of T-EMS algorithm (high complexity in the Check Node (CN) processor, wiring congestion due to the high number of exchanged messages between processors and the inability to implement decoders over high-order Galois fields due to the high decoder complexity), it was selected as starting point for this thesis due to its capability to reach high-throughput.Taking into account the identified limitations of the T-EMS algorithm, the second part of the thesis includes six papers with the results of the research made in order to mitigate the T-EMS disadvantages, offering solutions that reduce the area, the latency and increase the throughput compared to previous proposals from literature without sacrificing coding gain. Specifically, five low-complexity decoding algorithms are proposed, which introduce simplifications in different parts of the decoding process. Besides, five complete decoder architectures are designed and implemented on a 90nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The results show an achievement in throughput higher than 1Gbps and an area less than 10 mm 2 . The increase in throughput is 120% and the reduction in area is 53% compared to previous implementations of T-EMS, for the (837,726) NB-LDPC code over GF(32). The proposed decoders reduce the CN area, latency, wiring between CN and Variable Node (VN) processor and the number of storage elements required in the decoder. Considering that these proposals improve both area and speed, the efficiency parameter (Mbps / Million iii NAND gates) is increased in almost five times compared to other proposals from literature.The improvements in terms of area allow us to implement NB-LDPC decoders over high-order fields which had not been possible until now due to the highcomplexity of decoders previously proposed in literature. Therefore, we present the first post-place and route report for high-rate codes over high-order fields higher than Galois Field (GF)(32). For example, for the (1536,1344) NB-LDPC code over GF (64) ResumenEn esta tesis se aborda el estudio del diseño de algoritmos de baja complejidad para la decodificación de códigos de comprobación de paridad de baja densidad no binarios (NB-LDPC) y sus correspondientes arquitecturas apropiadas para decodificar códigos de alta tasa a altas velocidades (cientos de Mbps y Gbps).En la primera parte de la tesis los principales aspectos concernientes a los códi-gos NB-LDPC s...

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Low-complexity decoding for non-binary LDPC codes in high order fields

Cited by 199 publications

References 17 publications

Design of Spatially Coupled LDPC Codes Over GF $(q)$ for Windowed Decoding

Design of Spatially Coupled LDPC Codes Over GF $(q)$ for Windowed Decoding

High throughput and low complexity implementation of NB-LDPC decoder based on EMS algorithm

VLSI algorithms and architectures for non-binary-LDPC decoding

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