Low complexity FPGA implementation of Register Exchange Based Viterbi decoder

This paper presents the technique for designing the area efficient trellis code modulation encoder and decoder. One of the best encoding techniques is convolutional encoding as convolutional encoding improves the error performance of communicational channel. The trellis code modulation (TCM) can achieve the better error performance without Bandwidth expansion. Viterbi decoder is use in Trellis code modulation, to decode a data which is encoded by a convolutional encoder. Here TCM encoder and decoder are designed by using Xilinx ISE 13.2 design software and device use is Spartan 6. Proposed technique is aims to reduce the hardware requires for designing the TCM decoder by using hybrid register exchange method. Hybrid register exchange method (HREM) is a combination of the register exchange method (REM) and Traceback (TB) technique. HREM is superior as compared to Register Exchange Method (REM) and Traceback method (TB), where area requires for designing of survivor memory unit is more as compare to the proposed technique.

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Pruning the algorithm complexity of the Add-Compare Select Unit (ACSU) for the Viterbi Decoder - A Review

Rashid

Harun

Mansor

et al. 2018

2018 IEEE 5th International Conference on Smart Instrumentation, Measurement and Application (ICSIMA)

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Low complexity FPGA implementation of Register Exchange Based Viterbi decoder

Cited by 3 publications

References 4 publications

FPGA Implementation of FSM based Viterbi Decoder

FPGA Implementation of FSM based Viterbi Decoder

Design of Trellis code modulation decoder using Hybrid Register Exchange Method

Pruning the algorithm complexity of the Add-Compare Select Unit (ACSU) for the Viterbi Decoder - A Review

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