Low complexity hardware implementation of quantization and CAVLC for H.264 encoder

Joshi, Amit M.; Mishra, Vivekanand; Patrikar, Rajendra M.

doi:10.1109/iccic.2014.7238382

Cited by 3 publications

(1 citation statement)

References 16 publications

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“…The HDL (in our work VHDL) code is written for hardware implementation of anti‐notch IIR filter design, which is used for verification (functional simulation), FPGA synthesis, FPGA implementation, and ASIC synthesis of proposed hardware ANF filter 38 . The proposed design is synthesized using Xilinx ISE 14.4 for Zynq‐series (Zybo board with “xc7z010‐3‐clg400” device) FPGA family.…”

Section: Resultsmentioning

confidence: 99%

Hardware implementation of infinite impulse response anti‐notch filter for exon region identification in eukaryotic genes

Pathak

Nanda

Joshi

et al. 2020

Circuit Theory & Apps

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The discrimination of exons from introns in the DNA sequence of a eukaryotic gene is important to understand the functionality of protein formation inside a living organism. Several signal processing techniques involving transforms and filtering have been used to identify the exon regions by exploring the periodicity-3 property. Fast processing of massive DNA sequences is desirable to detect the disease-causing mechanism, which is helpful to prepare individual-centric drugs. In this manuscript, a hardware implementation is carried out for the direct form-II structure of the infinite impulse response anti-notch filter to achieve the fast processing of the DNA sequence. Implementation result on Zynq-series (Zybo board) Field Programmable Gate Array (FPGA) reveals that the proposed implementation is capable to identify the exon regions of five benchmark eukaryotic genes. The FPGA implementation has achieved a maximum clock frequency of 34.629 MHz, which is further improved to 54.41 MHz using the retiming concept. Compared with MATLAB 2014a simulation, the proposed FPGA implementation has achieved similar accuracy with 39 to 43 times faster computing time for the five benchmark data sets. Further, an Application Specific Integrated Circuit (ASIC) implementation is carried out in the CADENCE Register Transfer Level (RTL) compiler tool with GPDK 90-nm technology, due to which the hardware antinotch filter is 120 to 133 times faster compared with its MATLAB counterpart while maintaining the comparable accuracy.

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Section: Resultsmentioning

confidence: 99%

Hardware implementation of infinite impulse response anti‐notch filter for exon region identification in eukaryotic genes

Pathak

Nanda

Joshi

et al. 2020

Circuit Theory & Apps

View full text Add to dashboard Cite

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An efficient VLSI design of CAVLC encoder

Mukherjee

Banerjee

Maulik

et al. 2017

TENCON 2017 - 2017 IEEE Region 10 Conference

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High-Performance 32-Bit Parallel Hybrid Adder Design Using RNS and Hybrid PTL/CMOS Logic

Khairnar

Chauhan

Sharma

et al. 2022

J CIRCUIT SYST COMP

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Adders are one of the essential blocks of Arithmetic Logic Unit (ALU), addressing the memory, table indices and many more such types of applications. The speed of the adder unit more often decides the performance of CPU (Central Processing Unit) and GPU (Graphics Processing Unit) for graphics applications. The high-speed design is a very important performance parameter speed that too with less implementation area and low power consumption. In this paper, the author proposes a novel 32-bit Residue Hybrid Adder (RHA) using the Residue Number System (RNS) and implemented using a Hybrid CMOS/PTL logic style. An RNS has the advantage of representing a large integer using a set of few smaller integers to make computation more efficient and effective. On the other side, parallel prefix adders provide faster execution time as it performs the operation in parallel. With our paper, it is evident that RHA gives better performance in terms of delay, power consumption and area for arithmetic operations. The experimental analysis has been performed using the EDA tool on 45-nm CMOS technology. The power, delay and power delay product (PDP) performance parameters are compared with the existing adders and the results show that, thanks to smaller modules, proposed units have both smaller area and delay by up to 45% and 41%, and, consequently, they allow achieving up to over 46% power saving, respectively.

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Low complexity hardware implementation of quantization and CAVLC for H.264 encoder

Cited by 3 publications

References 16 publications

Hardware implementation of infinite impulse response anti‐notch filter for exon region identification in eukaryotic genes

Hardware implementation of infinite impulse response anti‐notch filter for exon region identification in eukaryotic genes

An efficient VLSI design of CAVLC encoder

High-Performance 32-Bit Parallel Hybrid Adder Design Using RNS and Hybrid PTL/CMOS Logic

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