Low‐complexity, high‐speed multi‐size cyclic‐shifter for quasi‐cyclic LDPC decoder

Kang, Hyeong-Ju; Yang, Byung‐Do

doi:10.1049/el.2017.4456

Cited by 5 publications

(5 citation statements)

References 10 publications

(22 reference statements)

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“…We also consider the maximum shift size P and the quantization bits in the normalization. From the normalized results, it is confirmed that the proposed solution helps reduce the complexity in comparison to the works introduced in [16,23,24]. Specifically, the area reduction from the RIP structure [23], the fine-coarse architecture with MUXs network [16], and the fine-coarse structure with RIP network [24] are 56.75%, 18.87%, and 49.75%, respectively.…”

Section: Implementation Results and Comparisonmentioning

confidence: 72%

“…To achieve the final circular shift message, each Z m -message from the first to the Z p th main rotator block is sequentially routed to the output of the MSCS network. To confirm the efficiency of our solution, we have compared the conventional RIP structure [23], the fine-coarse architecture with MUXs network [16], the fine-coarse structure with RIP network [24] with our proposed MCSN network for multi-size message passing network of the 5G LDPC decoder where the full lifting set Z is given by {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, 384}. The proposed MCSN network structures are synthesized using the TSMC 65-nm CMOS technology.…”

Section: Proposed Low-complexity Multi-size Circular-shift Networkmentioning

confidence: 99%

“…Specifically, the equivalent number of 2-to-1 MUXs is log 2 g × P + (P g − 1) × P , where the first term and the second term are for the pre-rotators and the MUX network, respectively. In [19,24], the MUX network in the AN is substituted with the Benes network and the RIP structure, respectively, to enhance the complexity of the MSCS network block.…”

Section: Multi-size Circular-shift Networkmentioning

confidence: 99%

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Low-Complexity Multi-Size Circular-Shift Network for 5G New Radio LDPC Decoders

Tan

Nguyen

Lee

2022

Sensors

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This paper presents a low-complexity multi-size circular-shift network (MCSN) structure for 5th-generation (5G) New Radio (NR) quasi-cyclic low-density parity-check (QC-LDPC) decoders. In particular, a fine-coarse approach-based multi-size cyclic shift network, which decomposes the cyclic shift size into fine part and coarse part, is introduced. The proposed MCSN structure is composed of a pre-rotator performing the fine part of the cyclic shift, and a main rotator executing the coarse part of the cyclic shift. In addition, a forward routing circular-shift (FRCS) network, which is based on the barrel shifter and the forward routing process is presented. The proposed switch network is able to support all 51 different submatrix sizes as defined in the 5G NR standard through an efficient forward routing switch network and help reduce the hardware complexity using a cyclic shift size decomposition method. The proposed MCSN is analyzed, and indicates a substantial reduction in the hardware complexity. The experimental results on TSMC 65-nm CMOS technology show that the proposed MCSN structure for 5G NR LDPC decoder offers an area saving up to 56.75% compared to related works in the literature.

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Section: Implementation Results and Comparisonmentioning

confidence: 72%

Section: Proposed Low-complexity Multi-size Circular-shift Networkmentioning

confidence: 99%

Section: Multi-size Circular-shift Networkmentioning

confidence: 99%

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Low-Complexity Multi-Size Circular-Shift Network for 5G New Radio LDPC Decoders

Tan

Nguyen

Lee

2022

Sensors

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“…A CS96 shifter is designed as a two-stage shifter as in [11,44], where the first stage is a pre-rotator network and the second stage is a QSN (abbreviated from QC-LDPC Shift Network) circular shifter [45]. As stated in (20), the 5G NR lifting size can take values of the form Z = a•2 j , where j goes from 0 for smallest to 7 for largest lifting sizes.…”

Section: Circular Shifting Network For High Flexibilitymentioning

confidence: 99%

Flexible 5G New Radio LDPC Encoder Optimized for High Hardware Usage Efficiency

2021

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Quasi-cyclic low-density parity-check (QC–LDPC) codes are introduced as a physical channel coding solution for data channels in 5G new radio (5G NR). Depending on the use case scenario, this standard proposes the usage of a wide variety of codes, which imposes the need for high encoder flexibility. LDPC codes from 5G NR have a convenient structure and can be efficiently encoded using forward substitution and without computationally intensive multiplications with dense matrices. However, the state-of-the-art solutions for encoder hardware implementation can be inefficient since many hardware processing units stay idle during the encoding process. This paper proposes a novel partially parallel architecture that can provide high hardware usage efficiency (HUE) while achieving encoder flexibility and support for all 5G NR codes. The proposed architecture includes a flexible circular shifting network, which is capable of shifting a single large bit vector or multiple smaller bit vectors depending on the code. The encoder architecture was built around the shifter in a way that multiple parity check matrix elements can be processed in parallel for short codes, thus providing almost the same level of parallelism as for long codes. The processing schedule was optimized for minimal encoding time using the genetic algorithm. The optimized encoder provided high throughputs, low latency, and up-to-date the best HUE.

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“…However, the controller is complicated because the control signals for a huge number of switch elements need to be generated in real time. Solutions [7][8] are built from a barrel shifter. Two shifters are employed, one shifts the input data to the right and another one shifts to the left.…”

Section: Introductionmentioning

confidence: 99%

Segmented Reconfigurable Cyclic Shifter for QC-LDPC Decoder

Lam

Qiu

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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In various wireless communication standards, such as Wi-Fi, WiMAX, and 5G standards, QC-LDPC decoders are required to decode a codeword of variable length. Part of the decoder is in idle if the length of codeword is not the maximum. A reconfigurable cyclic shifter is a key element of a QC-LDPC decoder. If the shifter can only shift one input at a time, the QC-LDPC decoder can only decode one codeword at a time as well. A segmented reconfigurable cyclic shifter is proposed in this paper to enable a QC-LDPC decoder to parallelly decode multiple codewords. The proposed shifter can be reconfigured into multiple segments of different sizes. Each segment can perform a cyclic shift of different shift values independently. Therefore, the proposed shifter can enhance the QC-LDPC decoder to decode multiple codewords parallelly by inputting another codeword (or codewords) to re-activate the idle hardware. The test chip of QC-LDPC decoder with the proposed segmented reconfigurable cyclic shifter has been fabricated in 0.18-μm CMOS technology which can parallelly decode six codewords.

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Low‐complexity, high‐speed multi‐size cyclic‐shifter for quasi‐cyclic LDPC decoder

Cited by 5 publications

References 10 publications

Low-Complexity Multi-Size Circular-Shift Network for 5G New Radio LDPC Decoders

Low-Complexity Multi-Size Circular-Shift Network for 5G New Radio LDPC Decoders

Flexible 5G New Radio LDPC Encoder Optimized for High Hardware Usage Efficiency

Segmented Reconfigurable Cyclic Shifter for QC-LDPC Decoder

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