Low Complexity Multiply Accumulate Unit for Weight-Sharing Convolutional Neural Networks

Abstract

Convolutional Neural Networks (CNNs) are one of the most successful deep machine learning technologies for processing image, voice and video data. CNNs require large amounts of processing capacity and memory, which can exceed the resources of low power mobile and embedded systems. Several designs for hardware accelerators have been proposed for CNNs which typically contain large numbers of Multiply Accumulate (MAC) units. One approach to reducing data sizes and memory traffic in CNN accelerators is "weight sharing", where the full range of values in a trained CNN are put in bins and the bin index is stored instead of the original weight value. In this paper we propose a novel MAC circuit that exploits binning in weight-sharing CNNs. Rather than computing the MAC directly we instead count the frequency of each weight and place it in a bin. We then compute the accumulated value in a subsequent multiply phase. This allows hardware multipliers in the MAC circuit to be replaced with adders and selection logic. Experiments show that for the same clock speed our approach results in fewer gates, smaller logic, and reduced power. Index Terms-Convolutional neural network, power efficiency, multiply accumulate, arithmetic hardware circuits.!

HOBFLOPS for CNNs: Hardware Optimized Bitslice-Parallel Floating-Point Operations for Convolutional Neural Networks

“…Garland et al, [11] show that they can vary the bit-width of their parallel accumulate shared MAC (PASM) between 4-bit and 32-bit in ASIC and maintain performance and accuracy while reducing power and area of the multiplier. In their follow up work, Garland et al, [12] show PASM can be implemented on an FPGA and vary the bit-width between INT8 and 32-bit, saving significant energy with only a slight increase in latency and no change in classification accuracy.…”

Low Complexity Multiply-Accumulate Units for Convolutional Neural Networks with Weight-Sharing

“…The 16-PAS-4-MAC also consumes 61% less leakage power, 70% less dynamic power and 70% less total power ( Figure 10). More details can be found in our original paper, [Garland and Gregg 2017].…”

Quadruple throughput fixed point quarter precision multiply accumulate circuit design

“…1c are not used during 16 × 16 bit MAC mode. In most of the non-vector MAC designs [6][7][8][18][19][20][21], the flexibility to perform multiple MAC operations is absent. For example, second, third, and fourth quarters of Figs.…”

“…In [20], the previous MAC result is added along with the sum and carry from the last carry save stage of the Wallace tree multiplier. In [21], memory‐based conventional MAC is designed, where one of the operand will be sent to the multiplier from the memory. In most of the above‐mentioned existing bits vector MACs ([14–16]), the hardware utilisation is less during bits or bits mode of operations.…”