Low-Complexity Online Synthesis for AMIDAR Processors

Abstract

Future chip technologies will change the way we deal with hardware design. First of all, logic resources will be available in vast amount. Furthermore, engineering specialized designs for particular applications will no longer be the general approach as the nonrecurring expenses will grow tremendously. Reconfigurable logic has often been promoted as a solution to these problems. Today, it can be found in two varieties: field programmable gate arrays or coarse-grained reconfigurable arrays. Using this type of technology typically requires a lot of expert knowledge, which is not sufficiently available. Thus, we believe that online synthesis that takes place during the execution of an application is one way to broaden the applicability of reconfigurable architectures. In this paper, we show that even a relative simplistic synthesis approach with low computational complexity can have a strong impact on the performance of compute intensive applications.

Synthilation: JIT-compilation of microinstruction sequences in AMIDAR processors

“…Yet, only very short basic blocks are taken into consideration, delivering only very limited application speedups. In AMIDAR processors, full loop bodies even with conditional execution paths can be transformed into configurations of reconfigurable hardware in the form of a CGRA [8] [9]. It should be noted that not all potential code sequences can be mapped to the CGRA and also that in some cases no acceleration will result from a mapping to the CGRA.…”

Exploring Online Synthesis for CGRAs with Specialized Operator Sets

“…Hence, we are trading quality of the synthesis results for a better performance and a smaller memory footprint. We have proposed our synthesis algorithms in previous work [4,5]. Anyhow, Section 5 details the synthesis as the algorithms are fundamental to our whole concept and the contributions of this article.…”