Low‐cost and high‐speed hardware implementation of contrast‐preserving image dynamic range compression for full‐HD video enhancement

Li, Shih‐An; Tsai, Chi-Yi

doi:10.1049/iet-ipr.2014.0162

Cited by 10 publications

(3 citation statements)

References 23 publications

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“…Furthermore, one has to consider the complex trade-off between performance, hardware (HW) resources, and efficiency degradation in terms of HW design. Li and Tsai [46] proposed the implementation of lowcost and high-speed HW for contrast-preserving and dynamic range compression. However, the Gaussian filter used in their algorithm can take only a small size.…”

Section: B Real Time Hardware Implementationsmentioning

confidence: 99%

An Efficient In-Memory Computing Architecture for Image Enhancement in AI Applications

et al. 2022

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Random Spray Retinex (RSR) is an effective image enhancement algorithm due to its effectiveness in improving image quality. However, the algorithm computing complexity and the required hardware resources and memory accesses hampered its deployment in many applications scenarios, for instance in IoT systems with limited hardware resources. With the rise of Artificial Intelligence (AI), the use of image enhancement has become essential to improve the performance for many emerging applications. In this paper, we propose the use of the RSR as a pre-processing filter before the task of semantic segmentation of low-quality urban road scenes. Using the publicly available Cityscapes dataset, we compare the performance of a pre-trained deep semantic segmentation network on dark noisy images and on RSR pre-processed images. Our findings confirm the effectiveness of RSR in improving segmentation accuracy. In addition, to address the computation complexity and suitability to edge devices, we propose a novel efficient implementation of the RSR using resistive random access memory (RRAM) technology. The architecture provides highly parallel analog in-memory computing (IMC) capabilities. A detailed, efficient and low latency implementation of the RSR using RRAM-CMOS technology is described. The design is verified using SPICE simulations with measured data from fabricated RRAM and 65nm CMOS technologies. The approach provided here represents an important step towards low-complexity and realtime hardware-friendly architecture and design for Retinex algorithms for edge devices.

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Section: B Real Time Hardware Implementationsmentioning

confidence: 99%

An Efficient In-Memory Computing Architecture for Image Enhancement in AI Applications

et al. 2022

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“…Li et al [26] presented a FPGA hardware implementation of a contrastpreserving image dynamic range compression algorithm. The FPGA implementation is a hardware-friendly approximation to the existing FDRCLCP algorithm [67], and used a line buffer instead of a frame buffer to process whole image data.…”

Section: Field Programmable Gate Arraymentioning

confidence: 99%

Real-time Tone Mapping: A State of the Art Report

Ou,

Ambalathankandy,

Ikebe

et al. 2020

Preprint

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The rising demand for high quality display has ensued active research in high dynamic range (HDR) imaging, which has the potential to replace the standard dynamic range imaging. This is due to HDR's features like accurate reproducibility of a scene with its entire spectrum of visible lighting and color depth. But this capability comes with expensive capture, display, storage and distribution resource requirements. Also, display of HDR images/video content on an ordinary display device with limited dynamic range requires some form of adaptation. Many adaptation algorithms, widely known as tone mapping operators, have been studied and proposed in the last few decades. In this state of the art report, we present a comprehensive survey of 50+ tone mapping algorithms that have been implemented on hardware for acceleration and real-time performance. These algorithms have been adapted or redesigned to make them hardware-friendly. This effort leads to various design challenges that are encountered during the hardware development. Any real-time application poses strict timing constraints which requires time exact processing of the algorithm. Also, most of the embedded systems would have limited system resources in terms of battery, computational power and memory resources. These design challenges require novel solutions, and in this report we focus on these issues.In this we survey will discuss those tonemap algorithms which have been implemented on GPU [1-10], FPGA , and ASIC [42][43][44][45][46][47][48][49][50][51][52][53] in terms of their hardware specifications and performance. Output image quality is an important metric for tonemap algorithms. From our literature survey we found that, various objective quality metrics have been used to demonstrate the functionality of adapting the algorithm on hardware platform. We have compiled and studied all the metrics used in this survey [54][55][56][57][58][59][60][61][62][63][64][65][66][67]. Finally, in this report we demonstrate the link between hardware cost and image quality thereby illustrating the underlying trade-off. This report concludes with a discussion on the general future research directions based-on various hardware design/implementation bottlenecks which will be useful for the research community.

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“…The proposed approach can be used in digital image processing [18], digital audio processing [19], medical imaging [20], hardware implementation of neural network architectures [21] and others.…”

Section: Introductionmentioning

confidence: 99%

High-Performance Digital Filtering on Truncated Multiply-Accumulate Units in the Residue Number System

et al. 2020

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Low‐cost and high‐speed hardware implementation of contrast‐preserving image dynamic range compression for full‐HD video enhancement

Cited by 10 publications

References 23 publications

An Efficient In-Memory Computing Architecture for Image Enhancement in AI Applications

An Efficient In-Memory Computing Architecture for Image Enhancement in AI Applications

Real-time Tone Mapping: A State of the Art Report

High-Performance Digital Filtering on Truncated Multiply-Accumulate Units in the Residue Number System

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