Low Cost Heterogeneous ARIA S-Box Implementation for CPA-Resistance

Abstract

Implementing countermeasure against power analysis-based attack is a critical issue in cryptographic hardware implementation. Protection schemes such as masking or Threshold Implementation (TI) have been proposed for hardware protection, but they have shortages like insufficient protection ability, or excessive hardware overhead. In this paper, we present low cost hetero S-box hardware implementation, where S-box groups for ARIA algorithm can be implemented using the coefficients with different hardware cost. Additional area reduction scheme using isomorphism sharing between S-boxes are also proposed. The proposed heterogeneous ARIS S-box has been implemented using 28nm CMOS process, and it showed 39% area saving with 30% of power saving. The proposed hardware also passed the security test, showing that it is verified as secure against power analysisbased attacks.