Low Cost Reversible Signed Comparator

Sharmin, Farah; Mitra, Rajib Kumar; Hasan, Rashida; Rahman, Anisur

doi:10.5121/vlsic.2013.4502

Cited by 11 publications

(4 citation statements)

References 20 publications

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“…Individual cell performance parameters analyze for reducing input voltage and finding power consumption, delay etc. [4] Y N N Available Circuit [3] N N Y Available Circuit [12] N N N Available Circuit [13] N N N Available Circuit [15] N N N Available Circuit [6] Y N N Available Circuit [5] Y…”

Section: Simulation Results and Discussionmentioning

confidence: 99%

“…It compares the 2-number of several bits. In this paper introduce group-based n-bit reversible comparator [6,9,11] and n-to-2 n reversible decoder with low value of reversible parameters with the help of various lemmas. This paper is organized with the following sections: Section 2 and 3 discuss basic definition of reversible logic; Section 4 discuss the past work; Section 5 discuss the utility and design issue of novel 4x4 inventive gate; Section 6 Planning of low value style reversible comparator subsection of 6.1 introduce novel 1-bit comparator cell, subsection 6.2 and 6.3 is novel match, larger and smaller comparator cell design; Subsection 6.4, 6.5, 6.6 and 6.7 for 2-bit, 8-bit, 32bit and n-bit group-based reversible comparator design respectively; Section 7 Implement all comparator cell in MOS transistor with minimum MOS transistor count.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Evolution of Structure of Some Binary Group-Based N-Bit Compartor, N-To-2N Decoder by Reversible Technique

Misra¹,

Wairya²,

Singh³

2014

VLSICS

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Section: Simulation Results and Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Evolution of Structure of Some Binary Group-Based N-Bit Compartor, N-To-2N Decoder by Reversible Technique

Misra¹,

Wairya²,

Singh³

2014

VLSICS

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“…This paper presents the design of n-bit reversible fault tolerant comparator. There are a few reversible comparators [6,7,8,9,10,11] but with number of garbage outputs being on the higher side. The proposed design outperforms the previous designs [8,10] in terms of garbage outputs and constant inputs.…”

Section: Introductionmentioning

confidence: 99%

Design of fault tolerant n bit reversible comparator for optimization of garbage and Ancilla bits

Jayashree

Agarwal

Charan

et al. 2014

International Conference on Circuits, Communication, Control and Computing

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Reversible logic is the emerging topic for research due to its advantage of low energy consumption. Fault tolerant circuit design is required to give error free outputs. In this paper we present an optimized n bit Reversible Fault Tolerant Comparator design using parity preserving reversible logic gates. The Design involves MSB comparison as the first stage followed by Next Bit comparison stage which contributes for 1 bit garbage-less comparator design. The Design is generalized for n bit comparison. The performance parameters are analyzed for n bit. Our work outperforms the existing reversible fault tolerant comparator designs in terms of garbage output and Ancilla inputs or constant inputs. This efficiency of our design helps in reducing the footprint of the design.

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“…YAG gate The input is represented as In={X, Y, Z} and the output is represented as Out={X, (X⊕Y)⊕(XY⊕Z), XY⊕Z}.YAG is used to realize AND and OR functions. Its block diagram is shown in Figure15[67].…”

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confidence: 99%

Reversible Logic Gates and Applications – A Low Power Solution to VLSI Chips

Tiwari,

Kadam,

Dudhedia

et al. 2024

MMEP

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In recent years, reversible logic gates have garnered significant interest because of their potential to decrease energy consumption and meet the growing need for low-power computing systems. Unlike conventional logic gates, reversible logic gates ensure that no information loss happens during computation, allowing for the reversal of the entire computation process. This unique characteristic opens up new avenues for developing energy-efficient digital circuits. This review paper serves as a vital contribution to the field by addressing a noticeable gap in the existing literature regarding reversible logic gates. The study not only comprehensively analyzes the array of reversible logic gates available but also underscores their practical applications and significance. It encompasses a wide variety of reversible logic gates, including Toffoli gates, Fredkin gates, and newer innovations. It is found that Toffoli gates outperformed in terms of gate count and quantum cost reduction, making them a preferred choice for quantum circuit optimization. Additionally, Fredkin gates showed exceptional performance in specific applications, like data swapping and quantum state control. The digital circuits like adders, multiplexers, ALU etc. are successfully designed using reversible gates like HNG, DKG etc. The significant gap this study fills lies in the need for a consolidated and in-depth analysis of the state-of-the-art reversible logic gates and their real-world utility. While prior research has discussed these gates individually, this paper takes a novel approach by offering a holistic assessment of their performance, quantum cost, gate count, and practical applications, thereby presenting a comprehensive resource for researchers, engineers, and designers in the field. This innovative contribution plays a pivotal role in shaping the progress of energy-efficient and quantum computing systems as well as in optimizing VLSI chip designs for various applications, with a particular emphasis on enhancing cryptographic and data processing capabilities. The findings of this review aim to stimulate further research and development in reversible computing, contributing to the advancement of energy-efficient and information-preserving computing systems.

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Low Cost Reversible Signed Comparator

Abstract: ABSTRACT

Cited by 11 publications

References 20 publications

Evolution of Structure of Some Binary Group-Based N-Bit Compartor, N-To-2N Decoder by Reversible Technique

Evolution of Structure of Some Binary Group-Based N-Bit Compartor, N-To-2N Decoder by Reversible Technique

Design of fault tolerant n bit reversible comparator for optimization of garbage and Ancilla bits

Reversible Logic Gates and Applications – A Low Power Solution to VLSI Chips

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