Low-Distortion Wideband Delta-Sigma ADCs With Shifted Loop Delays

Abstract

This paper presents several novel low-power low-distortion modulator topologies with shifted loop delays. Both single-sampled and double-sampled modulators are discussed. The proposed architectures can relax the critical timing for quantization and for dynamic element matching. A delay-free integrator in the last stage is used to perform the active summation, hence eliminating the active adder. The reduced input swing of the last integrator relaxes the OTA's requirements. The proposed topology simplifies the feed-forward paths, and saves power consumption and capacitor area. Noise-coupled technique can also be utilized to enhance the noise shaping. To verify the effect of the proposed topology, single-and double-sampled third-order modulators with and without noise coupling were analyzed and simulated.

A noise-coupled time-interleaved delta-sigma modulator with shifted loop delays

“…The most sensitive operation takes place at the input of the first integrator. The delay shifted from the first integrator to the input signal path is easily realized on the transistor level by holding half phase [5] or double sampling [7]. The delay in the input signal path helps to retain the low-distortion property.…”

Improved unity‐STF sturdy MASH ΣΔ modulator for low‐power wideband applications

“…2 b . A shifted loop delay technique [5], which moves the last integrator delay to the feedback path, is used to relax the DAC and DEM signal processing timing. To keep the low‐distortion property for the ΣΔM, the adder block in front of the quantiser is moved to the input of last integrator with an extra feedback path in modulator loop.…”