Low energy memory and register allocation using network flow

Gebotys, Catherine H.

doi:10.1145/266021.266192

Cited by 46 publications

(42 citation statements)

References 24 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…Ayala describes a combined hardware / software technique to detect portions of a program where a small number of register file entries are needed and the unneeded entries are disabled in hardware to save access energy [2]. Gebotys performs low-energy register and memory allocation by solving a minimum cost network flow [12]. This approach requires a complicated algorithm for allocation and we find little to no opportunity to improve the allocations resulting from our greedy algorithm.…”

Section: Related Workmentioning

confidence: 99%

A compile-time managed multi-level register file hierarchy

Gebhart

Keckler

Dally

2011

Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture

View full text Add to dashboard Cite

As processors increasingly become power limited, performance improvements will be achieved by rearchitecting systems with energy efficiency as the primary design constraint. While some of these optimizations will be hardware based, combined hardware and software techniques likely will be the most productive. This work redesigns the register file system of a modern throughput processor with a combined hardware and software solution that reduces register file energy without harming system performance. Throughput processors utilize a large number of threads to tolerate latency, requiring a large, energy-intensive register file to store thread context. Our results show that a compiler controlled register file hierarchy can reduce register file energy by up to 54%, compared to a hardware only caching approach that reduces register file energy by 34%. We explore register allocation algorithms that are specifically targeted to improve energy efficiency by sharing temporary register file resources across concurrently running threads and conduct a detailed limit study on the further potential to optimize operand delivery for throughput processors. Our efficiency gains represent a direct performance gain for power limited systems, such as GPUs.

show abstract

Section: Related Workmentioning

confidence: 99%

A compile-time managed multi-level register file hierarchy

Gebhart

Keckler

Dally

2011

Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture

View full text Add to dashboard Cite

show abstract

“…In Petrov and Orailoglu [13], the organization and power consumption of a translation look-aside buffer are adjusted on a per-application basis. In Gebotys [8], memory energy is managed through memory and register allocation using a network flow algorithm. In Ferrahi et al [7], a compiler technique to optimize sleep mode operation for memories is described.…”

Section: Related Workmentioning

confidence: 99%

Power-aware RAM mapping for FPGA embedded memory blocks

Tessier¹,

Betz²,

Neto³

et al. 2006

Proceedings of the 2006 ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays

View full text Add to dashboard Cite

Embedded memory blocks are important resources in contemporary FPGA devices. When targeting FPGAs, application designers often specify high-level memory functions which exhibit a range of sizes and control structures. These logical memories must be mapped to FPGA embedded memory resources such that physical design objectives are met. In this work a set of power-aware logical-to-physical RAM mapping algorithms are described which convert user-defined memory specifications to on-chip FPGA memory block resources. These algorithms minimize RAM dynamic power by evaluating a range of possible embedded memory block mappings and selecting the most power-efficient choice. Our automated approach has been integrated into a commercial FPGA compiler and tested with 40 large FPGA benchmarks. Through experimentation, we show that, on average, embedded memory dynamic power can be reduced by 21% and overall core dynamic power can be reduced by 7% with a minimal loss (1%) in design performance.

show abstract

“…If hottestedge represents a call edge (e.g., (6,8) in Figure 5), we will rely on the procedure InlineCriticalPaths available in alto [18] to inline a frequently executed subgraph rooted at the entry block of the callee. Afterwards, our algorithm will continue to grow the trace on the inlined subgraph as usual.…”

Section: Algorithmmentioning

confidence: 99%

A trace-based binary compilation framework for energy-aware computing

Xue

2004

Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems

View full text Add to dashboard Cite

Energy-aware compilers are becoming increasingly important for embedded systems due to the need to meet conflicting constraints on time, code size and power consumption. We introduce a trace-based, offline compiler framework on binaries and demonstrate its benefits in supporting energy optimisations. The key innovation lies in identifying frequently executed paths in a binary program and duplicating them as single-entry traces. Separating frequently from infrequently executed paths enables the compiler to focus both performance and energy optimisations on the hot traces.Traces constructed at the level of binaries are inherently inter-procedural, spanning both application and library code. Such a framework allows an embedded application developer to exploit optimisation opportunities made possible due to the information that is available only at link time.We describe the implementation of our trace-based framework in alto, a link-time optimiser for the Alpha architecture. We present a new algorithm for constructing the hot traces from binaries. This algorithm is both effective (since the execution cycles are mostly spent on traces) and practical (due to small code size increases caused). We have developed and implemented a new optimisation to reduce the functional unit leakage energy. We show how the traces facilitate the development of such an optimisation, which results in significant leakage energy savings for benchmark programs at the cost of small performance penalties.

show abstract

Low energy memory and register allocation using network flow

Cited by 46 publications

References 24 publications

A compile-time managed multi-level register file hierarchy

A compile-time managed multi-level register file hierarchy

Power-aware RAM mapping for FPGA embedded memory blocks

A trace-based binary compilation framework for energy-aware computing

Contact Info

Product

Resources

About