Low-error carry-free fixed-width multipliers with low-cost compensation circuits

Juang, Tso-Bing; Hsiao, Shen-Fu

doi:10.1109/tcsii.2005.848956

Cited by 45 publications

(45 citation statements)

References 8 publications

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“…18-µm CMOS standard cell library. It is seen from the synthesis results shown in Table 4 that the proposed truncated MBE multiplier occupies less silicon area compared to existing designs [7,8,11,12] and [13]. This is due to "non-generation" scheme used in the proposed algorithm, which reduces significant number of full adders and half adders used in partial product reduction.…”

Section: Resultsmentioning

confidence: 96%

“…The proposed truncated MBE multiplier and the FW multipliers used for comparison viz., Jou et al [7], Cho et al [8], Jiung and Hsiao [11], Van and Yang [12] and Wang et al [13] designs are described using structural VHDL to produce gate-level netlist and synthesized using Synopsys Design Compiler with TSMC. 18-µm CMOS standard cell library.…”

Section: Resultsmentioning

confidence: 99%

“…The novelty of the Alok, A. Katkar and James, E. Stine designs are that the total error in the final product is maintained within 1 unit of least significant bit. Juang and Hsiao [11] proposed a FW multiplier for signed numbers making little modification to the carry generation proposed in [8]. The author's proposed two circuits for compensation generation.…”

Section: Introductionmentioning

confidence: 99%

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VLSI Implementation of Area-Efficient Truncated Modified Booth Multiplier for Signal Processing Applications

Vijeyakumar¹,

Sumathy²,

Elango³

2014

Arab J Sci Eng

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In this paper, hardware efficient truncated multiplier using modified booth algorithm is proposed for signed bit multiplication, such that the average absolute error is kept minimum. The proposed methodology truncates the least significant bits (LSBs) of the final product and thus minimizes the number of full adders and half adders used in partial product accumulation. This we achieve by non-generation of an initial partial product and deletion of certain LSBs in higher order partial products. To minimize the error due to non generation and omission, we add compensation bits at appropriate retained bit positions. Experimental analysis of the proposed truncation algorithm implemented in modified booth encoded multiplier using Synopsys design compiler demonstrates area saving of nearly 25.1 % for an 8×8 design. The functionality of the proposed design is verified by implementing in a signal processing system.

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Section: Resultsmentioning

confidence: 96%

Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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VLSI Implementation of Area-Efficient Truncated Modified Booth Multiplier for Signal Processing Applications

Vijeyakumar¹,

Sumathy²,

Elango³

2014

Arab J Sci Eng

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“…The main disadvantage of this multiplier is circuit complexity is more. The Baugh Wooley multiplier is an efficient technique to handle the signed bit multiplication [6]. The Baugh Wooley technique is designed to direct multiplication of 2's complement numbers.…”

Section: Literature Surveymentioning

confidence: 99%

Empirical Analysis of Low Power and High Performance Multiplier

Hemavathi¹,

Rao²

2014

Computational Intelligence in Data Mining - Volume 2

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In this paper, A Modified Booth Recoding with Zero Bypassing technique for Low Power and High Performance Multiplier is proposed. In CMOS digital circuit design, the power and area are the main concerns. The proposed multiplier reduces the area and power consumption compared to the existing multipliers. In this paper, modified booth recoding technique and Encoder circuit and Zero bypassing Techniques are used. In this proposed multiplier, the numbers of partial products are reduced by using booth recoding with zero bypassing technique. The proposed multiplier is simulated and synthesized by using Xilinx 10.1 ISE design tool. The Total power is calculated by using XPower Analyzer.

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“…In order to further diminish the error, some schemes have been proposed where, instead of approximating the value of the partial products in LPminor by a constant, it is expressed as a function of the partial products in LPmajoor [4] gives an ECV for a modified Booth encoded PPA, where each line of partial products in LPminor is estimated as a multiple of the corresponding partial product in LPmajor (k = 1). This results in a data-dependent ECV.…”

Section: Introductionmentioning

confidence: 99%

Carry Prediction and Selection for Truncated Multiplication

Michard

Tisserand

Veyrat-Charvillon

2006

2006 IEEE Workshop on Signal Processing Systems Design and Implementation

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Abstract-This paper presents an error compensation method for truncated multiplication. From two n-bit operands, the operator produces an n-bit product with small error compared to the 2n-bit exact product. The method is based on a logical computation followed by a simplification process. The filtering parameter used in the simplification process helps to control the trade-off between hardware cost and accuracy. The proposed truncated multiplication scheme has been synthesized on an FPGA platform. It gives a better accuracy over area ratio than previous well-known schemes such as the constant correcting and variable correcting truncation schemes (CCT and VCT).

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Low-error carry-free fixed-width multipliers with low-cost compensation circuits

Cited by 45 publications

References 8 publications

VLSI Implementation of Area-Efficient Truncated Modified Booth Multiplier for Signal Processing Applications

VLSI Implementation of Area-Efficient Truncated Modified Booth Multiplier for Signal Processing Applications

Empirical Analysis of Low Power and High Performance Multiplier

Carry Prediction and Selection for Truncated Multiplication

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