Low-frequency noise characteristics of HfSiON gate-dielectric metal-oxide-semiconductor-field-effect transistors

Min, Bigang; Devireddy, Siva Prasad; Çelik‐Butler, Zeynep; Shanware, A.; Green, Keith; Chambers, James J.; Visokay, M. V.; Colombo, Luigi

doi:10.1063/1.1866507

Cited by 31 publications

(30 citation statements)

References 14 publications

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“…No significant differences in the spectra are noticed among the different Hf/Si ratios, indicating lower bulk defectivity for the silicates when compared to pure HfO 2 . Similar results are observed for p-MOSFETs and are in agreement with other recently published data [16].…”

Section: B the High-κ Layersupporting

confidence: 95%

High-k Gate Stack Engineering and Low Frequency Noise Performance

Luna-Sánchez

González-Martínez

2006

ECS Trans.

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Gate stack engineering for advanced deep submicron CMOS technology nodes has been extensively studied during the last decade, so that high-κ dielectrics in combination with metal gate or FUSI electrodes are implemented in several research lines. Much effort has been concentrated on the optimization of gate stacks from a viewpoint of dielectric properties and reliability issues. Less information is available on the low frequency noise performance of these gate stacks, which is an essential parameter for both analog and mixed signal applications. This review demonstrates the necessity of gate stack engineering for achieving a low 1/f noise performance. The impact of several processing parameters, such as the thickness of the interfacial layer and the high-κ oxide, bulk properties of the high-κ layer, post deposition anneal (PDA) treatments, choice of gate electrode material (poly-silicon, fully silicided or metal) will be addressed in order to point out the role of the different interfaces and bulk layers of the gate stack. Such a systematic study will form the basis for noise modeling as for these gate-dielectrics the standard noise models are no longer applicable. Finally, the impact on the noise behavior of strain engineering in the silicon substrate to boost up the carrier mobility is briefly discussed.

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Section: B the High-κ Layersupporting

confidence: 95%

High-k Gate Stack Engineering and Low Frequency Noise Performance

Luna-Sánchez

González-Martínez

2006

ECS Trans.

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“…It is known from the past that introduction of F in the gate oxide can reduce the density of active border traps (BTs) and interface states [11][12][13][14][15][16][17], which has recently also been validated for high-k-last pMOSFETs through LF noise studies [18]. the HfO 2 , layer is rather constant or slightly increases with depth, which is in line with past results on HfO 2 -based bulk planar MOSFETs [19][20][21][22][23]. However, it is shown here that post-deposition exposure to a F-containing plasma or to a post-deposition anneal (PDA) lowers the border trap density and at the same time changes the shape of the profile, evidencing the passivation of process-induced oxide traps by F [18,24] or its removal by a PDA.…”

Section: Introductionsupporting

confidence: 73%

Low-Frequency-Noise-Based Oxide Trap Profiling in Replacement High-k/Metal-Gate pMOSFETs

Simoen¹,

Lee²,

Veloso³

et al. 2013

ECS Trans.

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Low-frequency noise is studied in planar high-k-metal/gate (HKMG) last pMOSFETs in order to study the impact of a postHfO 2 deposition SF 6 -plasma or heat treatment on the oxide trap density and profile. It is shown that the gate oxide quality is improved by lowering the active border trap density for both approaches. At the same time, a detailed analysis of the frequency exponent of the flicker noise spectra reveals that in the case of the SF 6 -plasma, the reduction of the active border trap density occurs more efficiently deeper in the high-k layer, while the opposite holds for the annealed devices, i.e., a lower trap density is found closer to the interfacial SiO 2 layer.

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“…4e we compare the typical D ot extracted for our BPFETs with literature values for different technologies. [33][34][35][36][37][38][39][40] At room temperature the density of active oxide traps in our devices is~10 17 cm…”

Section: Resultsmentioning

confidence: 99%

Highly-stable black phosphorus field-effect transistors with low density of oxide traps

et al. 2017

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Black phosphorus is considered a very promising semiconductor for two-dimensional field-effect transistors. Initially, the main disadvantage of this material was thought to be its poor air stability. However, recent studies have shown that this problem can be solved by suitable encapsulation. As such, long-term studies of the outstanding properties of black phosphorus devices have become possible. In particular, here we examine highly-stable black phosphorus field-effect transistors and demonstrate that they can exhibit reproducible characteristics for at least 17 months. Furthermore, we notice some improvement in the performance of black phosphorus devices after this long time, i.e., positive aging. Although our black phosphorus devices are stable at room temperature, we show that their performance is affected by thermally activated charge trapping by oxide traps into the adjacent SiO 2 substrate layer. Aiming to analyze the dynamics of these defects in detail, we perform an accurate mapping of oxide traps with different time constants using the 'extended incremental hysteresis sweep method'. Our results show that at room temperature the extracted oxide trap densities are (i) few orders of magnitude lower than for MoS 2 /SiO 2 transistors and (ii) close to those reported for more mature Si/SiO 2 devices (~10 17 cm). Taking into account the novelty of black phosphorus and recent issues with its stability, these values must be considered unexpectedly low.

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Low-frequency noise characteristics of HfSiON gate-dielectric metal-oxide-semiconductor-field-effect transistors

Cited by 31 publications

References 14 publications

High-k Gate Stack Engineering and Low Frequency Noise Performance

High-k Gate Stack Engineering and Low Frequency Noise Performance

Low-Frequency-Noise-Based Oxide Trap Profiling in Replacement High-k/Metal-Gate pMOSFETs

Highly-stable black phosphorus field-effect transistors with low density of oxide traps

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