Low‐latency median filter core for hardware implementation of 5 × 5 median filtering

Kumar, Vineet; Asati, Abhijit; Gupta, Anu

doi:10.1049/iet-ipr.2016.0737

Cited by 25 publications

(6 citation statements)

References 18 publications

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“…Table 10 shows that the processing time increases as the variance value increases due to the increase in edge points. Aforementioned techniques [29, 30] will also reduce the processing time.…”

Section: Resultsmentioning

confidence: 99%

“…Therefore, in order to make the circle detection more accurate in noisy images, the image preprocessing and new edge map generation techniques need to be introduced to reduce false edges in the edge maps before applying CHT. Such techniques and their dedicated hardware implementations have been presented in our previous works [29, 30]. The processing time of the proposed CHT hardware in Table 10 was calculated using (5) and (6) for 100 images in a similar fashion as was done in Section 5.3.…”

Section: Resultsmentioning

confidence: 99%

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Memory‐efficient architecture of circle Hough transform and its FPGA implementation for iris localisation

Kumar¹,

Asati²,

Gupta³

2018

IET image process

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This study presents a circle Hough transform (CHT) architecture that provides memory reduction between 74 and 93% without and with little degradation in the accuracy, respectively. For an image of P × Q pixels, the standard (direct) CHT requires a two‐dimensional (2D) accumulator array of P × Q cells, but the proposed CHT uses a 2D accumulator array of (P/m) × (Q/n) cells for coarse circle detection and two 1D accumulator arrays of P × 1 and Q × 1 cells for fine detection, therein reducing the memory by a factor of m × n (approximately). The proposed CHT architecture was applied to iris localisation application and carried out its comprehensive evaluation. The average accuracy of the proposed CHT for iris localisation (inner plus outer iris‐circle detection) is 98% with memory reduction of 87% compared with the direct CHT. The proposed CHT architecture was implemented on field programmable logic array targeting Xilinx Zynq device. The proposed CHT hardware takes processing time of 6.25 ms (average) for iris localisation in an image of 320 × 240 px2. The proposed work is compared with the previous work, which shows improved results. Finally, the effect of additive Gaussian noise on the CHT performance is investigated.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Memory‐efficient architecture of circle Hough transform and its FPGA implementation for iris localisation

Kumar¹,

Asati²,

Gupta³

2018

IET image process

Self Cite

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“…Vineet kumar et al [17] proposed a design of efficient architecture for 5x5 processing window. Row and colomn sorting based approach implemented in five input sorter.…”

Section: Low Latency Filter(2017)mentioning

confidence: 99%

“…In ref [16] gaussian filter was proposed for efficiently reduce the latency by the compact architecture and error introduced adder which play the role major role in the circuit. In Ref [17] , new architecture was designed to estimate the median for the 25 input values.…”

Section: Introductionmentioning

confidence: 99%

Design of Low Power Architecture for Approximate Parallel Mid-Point Filter

Thiagarajan¹,

Vijeyakumar²,

Saravanakumar

2022

Preprint

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Approximate computing is a modern techniques for design of low power efficient arithmetic circuits for portable error resilient applications. In this work, we have proposed a Adaptive Parallel Mid-Point Filter (APMPF) architecture using proposed imprecise Max-Min Estimator (MME)targeting digital image processing. Parallel architecture for the MME can trade-off hardware at the expense of accuracy are proposed and used in the proposed APMPF. In APMPF, we use three level of sorting to estimate the mid-point of 3 x 3 window. Switching based trimmed filter is proposed for precise estimation of the selected window. Experimental Results interms of Area, Power and Delay with 90nm ASIC technology exposed that to the least, Proposed filters demonstrate 7% and 9% Area Delay Product (ADP) and Power Delay Product (PDP) reductions, respectively, compared to precise filter design.

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“…Therefore, it is necessary to reduce or remove the noise in the polluted image, which includes not only the external reasons such as uneven light source or incorrect acquisition method, but also the internal reasons of the system itself. In this paper, the median filter method [30][31] is used to process the image.…”

Section: Filtering Processingmentioning

confidence: 99%

Design and Implementation of Intelligent Image Detection System for Fertilizer Uniformity Based on Internet of Things

2022

DPS

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In agriculture, it is necessary to put fertilizer, which is conducive to the growth of crops. However, the amount of fertilizer must be strictly controlled, too much and too little will become the obstacles to the growth of crops. With the deepening of agricultural automation, the requirements of fertilizer put are more and more strict, so effective monitoring of the uniformity of fertilizer put is conducive to the good growth of crops. Aiming at the problem of fertilization uniformity detection, this paper designs an intelligent image detection system based on Internet of things technology. According to the actual needs, the system includes three modules: image acquisition, image transmission and image processing. Among them, the image acquisition module uses sensors to collect the land image after fertilization, the image transmission module uses network technology to transmit the collected image to the cloud, and the image processing module uses the good performance of convolution neural network to effectively extract the image characteristics and identify whether the uniformity of image fertilization is reasonable or not after image preprocessing. Through the simulation analysis, it shows that the intelligent image detection system based on the Internet of things can well detect whether the uniformity of fertilization is reasonable, improve the yield of crops, and promote the sustainable development of agricultural health.

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Low‐latency median filter core for hardware implementation of 5 × 5 median filtering

Cited by 25 publications

References 18 publications

Memory‐efficient architecture of circle Hough transform and its FPGA implementation for iris localisation

Memory‐efficient architecture of circle Hough transform and its FPGA implementation for iris localisation

Design of Low Power Architecture for Approximate Parallel Mid-Point Filter

Design and Implementation of Intelligent Image Detection System for Fertilizer Uniformity Based on Internet of Things

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