Low-latency Voltage-Racing Winner-Take-All (VR-WTA) circuit for acceleration of learning engine

Winner-Take-All and Loser-Take-All Circuits: Architectures, Applications and Analytical Comparison

“…where N and f refer to the number of inputs and maximum operating frequency, respectively. The viewpoint of low-voltage operation, the circuits presented in [28,43,47,48] are more promising, while the implementation presented in [43] has a relatively higher operating frequency. On the other hand, the TD circuit reported in [47] exhibits a lower voltage operation and, thus, a superior FoM.…”

“…In terms of speed, the circuits in [20,43] show better metrics. The configuration in [43] is capable of operating with a large number of inputs.…”

“…In terms of speed, the circuits in [20,43] show better metrics. The configuration in [43] is capable of operating with a large number of inputs. As a result, it exhibits better FoM, whereas the circuit in [20] is compact and more accurate.…”

“…Non-unique winners may also occur when more than one output becomes High. The combination reported in [43] is meant for the learning engine of the neural networks based on a parallel activity. In each cell, a linear delay element is used for converting the input voltage to a delayed pulse.…”

“…The time-domain WTA circuit illustrated in Figure 16a is presented in [47]. Here, the input signals control a reference clock The combination reported in [43] is meant for the learning engine of the neural networks based on a parallel activity. In each cell, a linear delay element is used for converting the input voltage to a delayed pulse.…”